f4pga-examples/projf-makefiles/hello/hello-arty/C
Joshua Fife d003ece145 fixed readmes and scripts to match #206
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
2021-10-29 23:22:04 -06:00
..
Makefile All part 1 designs 2021-10-28 13:45:15 -06:00
README.rst fixed readmes and scripts to match #206 2021-10-29 23:22:04 -06:00

README.rst

Part 1 Design C
===============

This design has the same functionality in hardware as part C but demonstrates
the use of conditional operators in System Verilog. To build this design run the 
following command in the main symbiflow directory:

.. code-block:: bash
   :name: hello-arty-c

   TARGET="arty_35" make -C projf-makefiles/hello/hello-arty/C

You can then download the bitstream by running:

.. code:: bash

   TARGET="arty_35" make download -C projf-makefiles/hello/hello-arty/C