65 lines
1.2 KiB
Systemverilog
65 lines
1.2 KiB
Systemverilog
`timescale 1ns / 1ps `default_nettype none
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module debounce (
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input wire logic clk,
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reset,
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noisy,
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output logic debounced
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);
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logic timerDone, clrTimer;
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typedef enum logic [1:0] {
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s0,
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s1,
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s2,
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s3,
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ERR = 'X
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} state_type_e;
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state_type_e ns, cs;
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logic [18:0] tA;
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timer #(.MOD_VALUE(500000), .BIT_WIDTH(19)) T0 (
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.clk(clk),
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.reset(clrTimer),
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.increment(1'b1),
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.rolling_over(timerDone),
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.count(tA)
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);
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always_comb begin
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ns = ERR;
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clrTimer = 0;
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debounced = 0;
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if (reset) ns = s0;
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else
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case (cs)
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s0: begin
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clrTimer = 1'b1;
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if (noisy) ns = s1;
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else ns = s0;
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end
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s1:
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if (noisy && timerDone) ns = s2;
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else if (noisy && ~timerDone) ns = s1;
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else ns = s0;
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s2: begin
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debounced = 1'b1;
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clrTimer = 1'b1;
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if (noisy) ns = s2;
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else ns = s3;
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end
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s3: begin
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debounced = 1'b1;
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if (~noisy && timerDone) ns = s0;
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else if (~noisy && ~timerDone) ns = s3;
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else ns = s2;
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end
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endcase
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end
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always_ff @(posedge clk) cs <= ns;
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endmodule
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