259 lines
6.8 KiB
Verilog
259 lines
6.8 KiB
Verilog
/*
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* PicoSoC - A simple example SoC using PicoRV32
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*
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* This is a modified PicoSoC example which has removed the requirement
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* for an external SPI flash. The PicoRV32 program is stored in ROM implemented
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* as a number of case statements. The ROM file is generated using an external
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* script.
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*
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*
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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`ifndef PICORV32_REGS
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`ifdef PICORV32_V
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`error "picosoc.v must be read before picorv32.v!"
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`endif
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`define PICORV32_REGS picosoc_regs
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`endif
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module picosoc_noflash (
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input clk,
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input resetn,
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output iomem_valid,
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input iomem_ready,
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output [ 3:0] iomem_wstrb,
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output [31:0] iomem_addr,
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output [31:0] iomem_wdata,
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input [31:0] iomem_rdata,
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input irq_5,
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input irq_6,
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input irq_7,
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output ser_tx,
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input ser_rx
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);
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parameter integer MEM_WORDS = 256;
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parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
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parameter [31:0] PROGADDR_RESET = 32'h 0010_0000; // 1 MB into flash
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reg [31:0] irq;
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wire irq_stall = 0;
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wire irq_uart = 0;
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always @* begin
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irq = 0;
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irq[3] = irq_stall;
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irq[4] = irq_uart;
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irq[5] = irq_5;
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irq[6] = irq_6;
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irq[7] = irq_7;
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end
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wire mem_valid;
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wire mem_instr;
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wire mem_ready;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [3:0] mem_wstrb;
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wire [31:0] mem_rdata;
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wire progmem_ready;
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wire [31:0] progmem_rdata;
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reg ram_ready;
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wire [31:0] ram_rdata;
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assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
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assign iomem_wstrb = mem_wstrb;
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assign iomem_addr = mem_addr;
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assign iomem_wdata = mem_wdata;
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wire spimemio_cfgreg_sel = mem_valid && (mem_addr == 32'h 0200_0000);
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wire simpleuart_reg_div_sel = mem_valid && (mem_addr == 32'h 0200_0004);
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wire [31:0] simpleuart_reg_div_do;
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wire simpleuart_reg_dat_sel = mem_valid && (mem_addr == 32'h 0200_0008);
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wire [31:0] simpleuart_reg_dat_do;
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wire simpleuart_reg_dat_wait;
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assign mem_ready =
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(iomem_valid && iomem_ready) || progmem_ready || ram_ready || spimemio_cfgreg_sel ||
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simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait);
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assign mem_rdata =
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(iomem_valid && iomem_ready) ? iomem_rdata :
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progmem_ready ? progmem_rdata :
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ram_ready ? ram_rdata :
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spimemio_cfgreg_sel ? 32'h0000_0000 : // Mockup, will always read 0
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simpleuart_reg_div_sel ? simpleuart_reg_div_do :
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simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : 32'h 0000_0000;
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`ifdef SIMULATION
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wire trace_valid;
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wire [35:0] trace_data;
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integer trace_file;
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`endif
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picorv32 #(
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.STACKADDR(STACKADDR),
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.PROGADDR_RESET(PROGADDR_RESET),
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.PROGADDR_IRQ(32'h 0000_0000),
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.BARREL_SHIFTER(1),
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.COMPRESSED_ISA(1),
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.ENABLE_MUL(1),
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.ENABLE_DIV(1),
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.ENABLE_IRQ(1),
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`ifdef SIMULATION
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.ENABLE_IRQ_QREGS(0),
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.ENABLE_TRACE(1)
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`else
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.ENABLE_IRQ_QREGS(0)
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`endif
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) cpu (
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.clk (clk ),
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.resetn (resetn ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata ),
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`ifdef SIMULATION
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.irq (irq ),
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.trace_valid (trace_valid),
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.trace_data (trace_data )
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`else
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.irq (irq )
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`endif
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);
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// This it the program ROM memory for the PicoRV32
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progmem progmem (
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.clk (clk),
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.rstn (resetn),
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.valid (mem_valid && mem_addr >= 4*MEM_WORDS && mem_addr < 32'h 0200_0000),
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.ready (progmem_ready),
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.addr (mem_addr),
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.rdata (progmem_rdata)
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);
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simpleuart simpleuart (
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.clk (clk ),
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.resetn (resetn ),
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.ser_tx (ser_tx ),
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.ser_rx (ser_rx ),
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.reg_div_we (simpleuart_reg_div_sel ? mem_wstrb : 4'b 0000),
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.reg_div_di (mem_wdata),
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.reg_div_do (simpleuart_reg_div_do),
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.reg_dat_we (simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b 0),
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.reg_dat_re (simpleuart_reg_dat_sel && !mem_wstrb),
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.reg_dat_di (mem_wdata),
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.reg_dat_do (simpleuart_reg_dat_do),
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.reg_dat_wait(simpleuart_reg_dat_wait)
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);
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always @(posedge clk)
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ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS;
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picosoc_mem #(.WORDS(MEM_WORDS)) memory (
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.clk(clk),
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.wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0),
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.addr(mem_addr[23:2]),
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.wdata(mem_wdata),
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.rdata(ram_rdata)
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);
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// Simulation debug
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`ifdef SIMULATION
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always @(posedge clk)
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if (resetn) begin
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if ( mem_instr && mem_valid && mem_ready)
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$display("Inst rd: [0x%08X] = 0x%08X", mem_addr, mem_rdata);
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if (!mem_instr && mem_valid && mem_ready)
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$display("Data rd: [0x%08X] = 0x%08X", mem_addr, mem_rdata);
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end
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// Trace
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initial begin
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trace_file = $fopen("testbench.trace", "w");
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repeat (10) @(posedge clk);
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while(1) begin
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@(posedge clk)
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if (resetn && trace_valid)
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$fwrite(trace_file, "%x\n", trace_data);
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$fflush(trace_file);
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//$display("Trace : %09X", trace_data);
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end
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end
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`endif // SIMULATION
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endmodule
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// Implementation note:
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// Replace the following two modules with wrappers for your SRAM cells.
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module picosoc_regs (
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input clk, wen,
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input [5:0] waddr,
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input [5:0] raddr1,
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input [5:0] raddr2,
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input [31:0] wdata,
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output [31:0] rdata1,
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output [31:0] rdata2
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);
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(* ram_style = "distributed" *) reg [31:0] regs [0:31];
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always @(posedge clk)
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if (wen) regs[waddr[4:0]] <= wdata;
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assign rdata1 = regs[raddr1[4:0]];
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assign rdata2 = regs[raddr2[4:0]];
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endmodule
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module picosoc_mem #(
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parameter integer WORDS = 256
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) (
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input clk,
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input [3:0] wen,
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input [21:0] addr,
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input [31:0] wdata,
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output reg [31:0] rdata
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);
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(* ram_style = "distributed" *) reg [31:0] mem [0:WORDS-1];
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always @(posedge clk) begin
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rdata <= mem[addr];
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if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
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if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];
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if (wen[2]) mem[addr][23:16] <= wdata[23:16];
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if (wen[3]) mem[addr][31:24] <= wdata[31:24];
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end
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endmodule
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