138 lines
3.4 KiB
Verilog
138 lines
3.4 KiB
Verilog
/*
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* PicoSoC - A simple example SoC using PicoRV32
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*
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module simpleuart (
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input clk,
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input resetn,
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output ser_tx,
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input ser_rx,
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input [3:0] reg_div_we,
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input [31:0] reg_div_di,
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output [31:0] reg_div_do,
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input reg_dat_we,
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input reg_dat_re,
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input [31:0] reg_dat_di,
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output [31:0] reg_dat_do,
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output reg_dat_wait
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);
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reg [31:0] cfg_divider;
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reg [3:0] recv_state;
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reg [31:0] recv_divcnt;
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reg [7:0] recv_pattern;
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reg [7:0] recv_buf_data;
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reg recv_buf_valid;
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reg [9:0] send_pattern;
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reg [3:0] send_bitcnt;
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reg [31:0] send_divcnt;
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reg send_dummy;
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assign reg_div_do = cfg_divider;
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assign reg_dat_wait = reg_dat_we && (send_bitcnt || send_dummy);
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assign reg_dat_do = recv_buf_valid ? recv_buf_data : ~0;
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always @(posedge clk) begin
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if (!resetn) begin
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cfg_divider <= 1;
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end else begin
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if (reg_div_we[0]) cfg_divider[ 7: 0] <= reg_div_di[ 7: 0];
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if (reg_div_we[1]) cfg_divider[15: 8] <= reg_div_di[15: 8];
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if (reg_div_we[2]) cfg_divider[23:16] <= reg_div_di[23:16];
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if (reg_div_we[3]) cfg_divider[31:24] <= reg_div_di[31:24];
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end
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end
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always @(posedge clk) begin
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if (!resetn) begin
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recv_state <= 0;
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recv_divcnt <= 0;
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recv_pattern <= 0;
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recv_buf_data <= 0;
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recv_buf_valid <= 0;
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end else begin
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recv_divcnt <= recv_divcnt + 1;
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if (reg_dat_re)
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recv_buf_valid <= 0;
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case (recv_state)
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0: begin
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if (!ser_rx)
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recv_state <= 1;
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recv_divcnt <= 0;
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end
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1: begin
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if (2*recv_divcnt > cfg_divider) begin
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recv_state <= 2;
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recv_divcnt <= 0;
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end
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end
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10: begin
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if (recv_divcnt > cfg_divider) begin
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recv_buf_data <= recv_pattern;
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recv_buf_valid <= 1;
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recv_state <= 0;
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end
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end
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default: begin
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if (recv_divcnt > cfg_divider) begin
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recv_pattern <= {ser_rx, recv_pattern[7:1]};
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recv_state <= recv_state + 1;
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recv_divcnt <= 0;
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end
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end
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endcase
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end
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end
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assign ser_tx = send_pattern[0];
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always @(posedge clk) begin
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if (reg_div_we)
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send_dummy <= 1;
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send_divcnt <= send_divcnt + 1;
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if (!resetn) begin
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send_pattern <= ~0;
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send_bitcnt <= 0;
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send_divcnt <= 0;
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send_dummy <= 1;
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end else begin
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if (send_dummy && !send_bitcnt) begin
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send_pattern <= ~0;
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send_bitcnt <= 15;
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send_divcnt <= 0;
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send_dummy <= 0;
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end else
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if (reg_dat_we && !send_bitcnt) begin
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send_pattern <= {1'b1, reg_dat_di[7:0], 1'b0};
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send_bitcnt <= 10;
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send_divcnt <= 0;
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end else
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if (send_divcnt > cfg_divider && send_bitcnt) begin
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send_pattern <= {1'b1, send_pattern[9:1]};
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send_bitcnt <= send_bitcnt - 1;
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send_divcnt <= 0;
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end
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end
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end
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endmodule
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