32 lines
871 B
Systemverilog
32 lines
871 B
Systemverilog
module top(
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input wire logic clk, btnc, rx_in,
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input wire logic[7:0] sw,
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output logic[7:0] segment,
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output logic[3:0] anode,
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output logic tx_debug, tx_out,
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output logic[4:0] debugLED
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);
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logic rx_error, rx_debug;
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logic busyByBy, tx_mid, send, btn[1:0];
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tx T0(.tx_out(tx_mid), .odd(1'b0), .busy(busyByBy), .din(sw), .clk(clk), .send(btn[1]),
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.state(debugLED));
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assign tx_out = tx_mid;
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assign tx_debug = tx_mid;
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logic busyByByRx, dataGoner, btnRx[1:0];
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logic[7:0] rx_data;
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rx R0(.rx_in(rx_in), .odd(1'b0), .busy(busyByByRx), .data_strobe(dataGoner),
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.dout(rx_data), .error(rx_error), .clk(clk));
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assign rx_debug = rx_in;
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SevenSegmentControl S1(.dataIn({rx_data[7:0],
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sw[7:0]}), .reset(0), .digitDisplay(4'hf), .digitPoint(4'h4), .anode(anode),
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.segment(segment), .clk(clk));
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always_ff @(posedge clk)
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btn[0] <= btnc;
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always_ff @(posedge clk)
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btn[1] <= btn[0];
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endmodule
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