mirror of
https://github.com/chipsalliance/f4pga-examples.git
synced 2025-01-03 03:43:38 -05:00
8ae95b0d8d
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
16 lines
602 B
Tcl
16 lines
602 B
Tcl
# Clock pin
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set_property PACKAGE_PIN W5 [get_ports {clk}]
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set_property IOSTANDARD LVCMOS33 [get_ports {clk}]
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# LEDs
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set_property PACKAGE_PIN U16 [get_ports {led[0]}]
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set_property PACKAGE_PIN E19 [get_ports {led[1]}]
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set_property PACKAGE_PIN U19 [get_ports {led[2]}]
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set_property PACKAGE_PIN V19 [get_ports {led[3]}]
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set_property IOSTANDARD LVCOMOS33 [get_ports {led[0]}]
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set_property IOSTANDARD LVCOMOS33 [get_ports {led[1]}]
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set_property IOSTANDARD LVCOMOS33 [get_ports {led[2]}]
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set_property IOSTANDARD LVCOMOS33 [get_ports {led[3]}]
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# Clock constraints
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create_clock -period 10.0 [get_ports {clk}]
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