f4pga-examples/xc7
Unai Martinez-Corral a46951037b requirements: bump f4pga
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
2022-07-31 20:08:01 +02:00
..
additional_examples xc7: use openFPGALoader instead of openocd 2022-07-05 10:00:08 +02:00
counter_test xc7/counter_test/Makefile: support F4PGA_USE_DEPRECATED 2022-06-22 13:41:15 +02:00
linux_litex_demo xc7/linux_litex_demo/README: do not use extlink 2022-03-15 12:25:05 +01:00
litex_demo xc7: use openFPGALoader instead of openocd 2022-07-05 10:00:08 +02:00
litex_sata_demo xc7: lite sata add third party code for VexRiscV and improve docs 2021-11-30 13:41:25 +01:00
picosoc_demo added symplified download instructions 2021-11-11 13:47:47 -07:00
pulse_width_led fixed minor issues 2021-11-11 13:50:34 -07:00
timer Raname to F4PGA 2022-02-18 18:15:44 +01:00
README.rst Raname to F4PGA 2022-02-18 18:15:44 +01:00
environment.yml xc7: update conda environment dependencies 2022-07-21 15:16:14 +02:00
requirements.txt requirements: bump f4pga 2022-07-31 20:08:01 +02:00

README.rst

F4PGA Toolchain Examples for Xilinx 7 Series
============================================

#. ``counter`` - simple 4-bit counter driving LEDs. The design targets the `Basys3 board <https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/>`__, the `Arty boards <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/>`__, and the `Zybo Z7 board <https://store.digilentinc.com/zybo-z7-zynq-7000-arm-fpga-soc-development-board/>`__
#. ``picosoc`` - `picorv32 <https://github.com/cliffordwolf/picorv32>`__ based SoC. The design targets the `Basys3 board <https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/>`__.
#. ``litex`` - Series of `LiteX-based <https://github.com/enjoy-digital/litex>`__ designs, that feature different CPU types and LiteX modules.
#. ``linux_litex`` - `LiteX <https://github.com/enjoy-digital/litex>`__ based system with Linux capable `VexRiscv core <https://github.com/SpinalHDL/VexRiscv>`__. The design includes `DDR <https://github.com/enjoy-digital/litedram>`__ and `Ethernet <https://github.com/enjoy-digital/liteeth>`__ controllers. The design targets the `Arty boards <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/>`__.

The Linux images for the ``linux_litex`` example can be built following the `linux on litex vexriscv <https://github.com/litex-hub/linux-on-litex-vexriscv>`__ instructions.
The ``linux_litex`` example is already provided with working Linux images.

The detailed description about building the examples is available in the
`project documentation <https://f4pga-examples.readthedocs.io/en/latest/building-examples.html#xilinx-7-series>`__.