abccf5f7ef
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com> |
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.github | ||
common | ||
docs | ||
eos-s3 | ||
projf-makefiles/hello/hello-arty | ||
scripts/make | ||
third_party | ||
xc7 | ||
.gitattributes | ||
.gitignore | ||
.gitmodules | ||
.readthedocs.yml | ||
.style.yapf | ||
LICENSE | ||
Makefile | ||
README.md |
README.md
F4PGA examples
This repository provides example FPGA designs that can be built using the F4PGA open source toolchain. These examples target the Xilinx 7-Series and the QuickLogic EOS S3 devices.
- Please refer to the for a proper guide on how to run these examples, as well as instructions on how to build and compile your own HDL designs using the F4PGA toolchain.
- See to contribute on the development of architecture support in F4PGA.
The repository includes:
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xc7/ and eos-s3/ - Examples for Xilinx 7-Series and EOS-S3 devices, including:
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Verilog code
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Pin constraints files
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Timing constraints files
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Makefiles for running the F4PGA toolchain
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docs/ - Guide on how to get started with F4PGA and build provided examples
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.github/ - Directory with CI configuration and scripts
The examples provided in this repository are automatically built and tested in CI by extracting necessary code snippets with tuttest.