48 lines
1.1 KiB
Systemverilog
48 lines
1.1 KiB
Systemverilog
`timescale 1ns / 1ps
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`default_nettype none
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module top(
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input wire logic clk, btnu, btnc,
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output logic[3:0] anode,
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output logic[7:0] segment
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);
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logic sync;
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logic syncToDebounce;
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logic debounceToOneShot;
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logic f1, f2;
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logic f3, f4;
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logic oneShotToCounter;
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logic[7:0] counterToSevenSegment;
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logic[7:0] counterToSevenSegment2;
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logic oneShotToCounter2;
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logic s0, s1;
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debounce d0(clk, btnu, syncToDebounce, debounceToOneShot);
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assign oneShotToCounter = f1 && ~f2;
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assign oneShotToCounter2 = f3 && ~f4;
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timer_par #(256, 8) T0(clk, btnu, oneShotToCounter, s0, counterToSevenSegment);
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timer_par #(256, 8) T1(clk, btnu, oneShotToCounter2, s1, counterToSevenSegment2);
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SevenSegmentControl SSC0 (clk, btnu, {counterToSevenSegment2, counterToSevenSegment}, 4'b1111, 4'b0000, anode, segment);
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always_ff @(posedge clk)
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begin
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sync <= btnc;
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syncToDebounce <= sync;
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f1 <= debounceToOneShot;
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f2 <= f1;
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f3 <= syncToDebounce;
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f4 <= f3;
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end
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endmodule
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