67 lines
2.1 KiB
Systemverilog
67 lines
2.1 KiB
Systemverilog
`default_nettype none
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module display_control (
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input wire logic clk,
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input wire logic reset,
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input wire logic [15:0] dataIn,
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input wire logic [ 3:0] digitDisplay,
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input wire logic [ 3:0] digitPoint,
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output logic [ 3:0] anode,
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output logic [ 7:0] segment
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);
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parameter integer COUNT_BITS = 17;
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logic [COUNT_BITS-1:0] count_val;
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logic [ 1:0] anode_select;
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logic [ 3:0] cur_anode;
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logic [ 3:0] cur_data_in;
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always_ff @(posedge clk) begin
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if (reset) count_val <= 0;
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else count_val <= count_val + 1;
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end
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assign anode_select = count_val[COUNT_BITS-1:COUNT_BITS-2];
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assign cur_anode =
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(anode_select == 2'b00) ? 4'b1110 :
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(anode_select == 2'b01) ? 4'b1101 :
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(anode_select == 2'b10) ? 4'b1011 :
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4'b0111;
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assign anode = cur_anode | (~digitDisplay);
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assign cur_data_in =
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(anode_select == 2'b00) ? dataIn[3:0] :
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(anode_select == 2'b01) ? dataIn[7:4] :
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(anode_select == 2'b10) ? dataIn[11:8] :
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dataIn[15:12] ;
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assign segment[7] =
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(anode_select == 2'b00) ? ~digitPoint[0] :
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(anode_select == 2'b01) ? ~digitPoint[1] :
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(anode_select == 2'b10) ? ~digitPoint[2] :
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~digitPoint[3] ;
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assign segment[6:0] =
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(cur_data_in == 0) ? 7'b1000000 :
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(cur_data_in == 1) ? 7'b1111001 :
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(cur_data_in == 2) ? 7'b0100100 :
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(cur_data_in == 3) ? 7'b0110000 :
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(cur_data_in == 4) ? 7'b0011001 :
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(cur_data_in == 5) ? 7'b0010010 :
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(cur_data_in == 6) ? 7'b0000010 :
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(cur_data_in == 7) ? 7'b1111000 :
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(cur_data_in == 8) ? 7'b0000000 :
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(cur_data_in == 9) ? 7'b0010000 :
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(cur_data_in == 10) ? 7'b0001000 :
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(cur_data_in == 11) ? 7'b0000011 :
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(cur_data_in == 12) ? 7'b1000110 :
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(cur_data_in == 13) ? 7'b0100001 :
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(cur_data_in == 14) ? 7'b0000110 :
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7'b0001110;
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endmodule
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