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17 lines
487 B
ReStructuredText
17 lines
487 B
ReStructuredText
Part 1 Design C
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===============
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This design has the same functionality in hardware as part C but demonstrates
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the use of conditional operators in System Verilog. To build this design run the
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following command in the main f4pga directory:
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.. code-block:: bash
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:name: hello-arty-c
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TARGET="arty_35" make -C projf-makefiles/hello/hello-arty/C
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You can then download the bitstream by running:
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.. code:: bash
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TARGET="arty_35" make download -C projf-makefiles/hello/hello-arty/C
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