Example designs showing different ways to use F4PGA toolchains.
Go to file
Rafal Kolucki d87ad8e14a docs: add instructions for K4N8
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
2022-12-02 17:30:50 +01:00
.github ci: avoid overwriting artifacts 2022-10-13 21:55:58 +02:00
common common/requirements: bump f4pga 2022-10-13 18:36:55 +02:00
docs docs: add instructions for K4N8 2022-12-02 17:30:50 +01:00
eos-s3 eos-s3/btn_counter/Makefile: add missing jlink dump 2022-08-04 07:29:46 +02:00
projf-makefiles/hello/hello-arty Raname to F4PGA 2022-02-18 18:15:44 +01:00
qlf_k4n8 qlf_k4n8: Add qlf_fasm to qlf_k4n8 environment 2022-12-02 17:30:50 +01:00
scripts/make Raname to F4PGA 2022-02-18 18:15:44 +01:00
third_party xc7: lite sata add third party code for VexRiscV and improve docs 2021-11-30 13:41:25 +01:00
xc7 xc7/counter_test: f4pga -vv build 2022-08-18 22:22:31 +02:00
.gitattributes update gitattributes 2020-06-09 22:16:32 +02:00
.gitignore changes after initial review 2021-05-13 12:07:04 -06:00
.gitmodules xc7: lite sata add third party code for VexRiscV and improve docs 2021-11-30 13:41:25 +01:00
.readthedocs.yml readthedocs: do not fail on warnings 2022-03-15 12:25:43 +01:00
.style.yapf changes after initial review 2021-05-13 12:07:04 -06:00
LICENSE Relicense to Apache-2.0 2022-02-02 19:41:06 +01:00
Makefile Raname to F4PGA 2022-02-18 18:15:44 +01:00
README.md Add demo for qlf-k4n8 2022-12-02 17:30:50 +01:00

README.md

F4PGA examples

'Doc' workflow status

This repository provides example FPGA designs that can be built using the F4PGA open source toolchain. These examples target the Xilinx 7-Series, the QuickLogic EOS S3 and K4N8 devices.

  • Please refer to the for a proper guide on how to run these examples, as well as instructions on how to build and compile your own HDL designs using the F4PGA toolchain.
  • See to contribute on the development of architecture support in F4PGA.

The repository includes:

  • xc7/, eos-s3/ and qlf_k4n8/- Examples for Xilinx 7-Series, EOS-S3 and K4N8 devices, including:

    • Verilog code

    • Pin constraints files

    • Timing constraints files

    • Makefiles for running the F4PGA toolchain

  • docs/ - Guide on how to get started with F4PGA and build provided examples

  • .github/ - Directory with CI configuration and scripts

The examples provided in this repository are automatically built and tested in CI by extracting necessary code snippets with tuttest.