20 lines
533 B
Systemverilog
20 lines
533 B
Systemverilog
`timescale 1ns / 1ps
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`default_nettype none
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module stopwatch(
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input wire logic clk, reset, run,
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output logic[3:0] digit0, digit1, digit2, digit3
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);
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logic inc0, inc1, inc2, inc3, inc4;
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logic[23:0] timerCount;
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mod_counter #(10) M0(clk, reset, inc0, inc1, digit0);
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mod_counter #(10) M1(clk, reset, inc1, inc2, digit1);
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mod_counter #(10) M2(clk, reset, inc2, inc3, digit2);
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mod_counter #(6) M3(clk, reset, inc3, inc4, digit3);
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timer #(1000000) T0(clk, reset, run, inc0, timerCount);
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endmodule
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