f4pga-examples/examples/eos-s3/btn_counter.v
Karol Gugala 9004f3d02f Add QuickLogic EOS-S3 example
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2020-06-10 00:00:47 +02:00

14 lines
195 B
Verilog
Vendored

module top(
input wire clk,
output wire [3:0] led
);
reg [3:0] cnt;
initial cnt <= 0;
always @(posedge clk)
cnt <= cnt + 1;
assign led = cnt;
endmodule