49 lines
2.1 KiB
Plaintext
49 lines
2.1 KiB
Plaintext
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Place & Route
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#############
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The Synthesis process results in an output containing logical elements
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available on the desired FPGA chip with the specified connections between them.
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However, it does not specify the physical layout of those elements in the
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final design. The goal of the Place and Route (PnR) process is to take the
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synthesized design and implement it into the target FPGA device. The PnR tool
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needs to have information about the physical composition of the device, routing
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paths between the different logical blocks and signal propagation timings.
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The working flow of different PnR tools may vary, however, the process presented
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below represents the typical one, adopted by most of these tools. Usually, it
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consists of four steps - packing, placing, routing and analysis.
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Packing
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=======
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In the first step, the tool collects and analyzes the primitives present
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in the synthesized design (e.g. Flip-Flops, Muxes, Carry-chains, etc), and
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organizes them in clusters, each one belonging to a physical tile of the device.
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The PnR tool makes the best possible decision, based on the FPGA routing
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resources and timings between different points in the chip.
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Placing
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=======
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After having clustered all the various primitives into the physical tiles of the
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device, the tool begins the placement process. This step consists in assigning a
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physical location to every cluster generated in the packing stage. The choice of
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the locations is based on the chosen algorithm and on the user's parameters, but
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generally, the final goal is to find the best placement that allows the routing
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step to find more optimal solutions.
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Routing
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=======
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Routing is one of the most demanding tasks of the whole process.
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All possible connections between the placed blocks and the information on
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the signals propagation timings, form a complex graph.
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The tool tries to find the optimal path connecting all the placed
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clusters using the information provided in the routing graph. Once all the nets
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have been routed, an output file containing the implemented design is produced.
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Analysis
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========
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This last step usually checks the whole design in terms of timings and power
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consumption.
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