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Supported Architectures</a>
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Community</a>
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<span class="md-nav__link caption"><span class="caption-text">Python utils</span></span>
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Overview</a>
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Usage</a>
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Place & Route</a>
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In F4PGA</a>
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FPGA Assembly (FASM) ➚</a>
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FPGA Interchange schema ➚</a>
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References</a>
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<li class="md-nav__item"><a href="#placing" class="md-nav__link">Placing</a>
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<section id="place-route">
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<h1 id="flows-pnr--page-root">Place & Route<a class="headerlink" href="#flows-pnr--page-root" title="Link to this heading">¶</a></h1>
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<p>The Synthesis process results in an output containing logical elements
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available on the desired FPGA chip with the specified connections between them.
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However, it does not specify the physical layout of those elements in the
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final design. The goal of the Place and Route (PnR) process is to take the
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synthesized design and implement it into the target FPGA device. The PnR tool
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needs to have information about the physical composition of the device, routing
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paths between the different logical blocks and signal propagation timings.
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The working flow of different PnR tools may vary, however, the process presented
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below represents the typical one, adopted by most of these tools. Usually, it
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consists of four steps - packing, placing, routing and analysis.</p>
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<section id="packing">
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<h2 id="packing">Packing<a class="headerlink" href="#packing" title="Link to this heading">¶</a></h2>
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<p>In the first step, the tool collects and analyzes the primitives present
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in the synthesized design (e.g. Flip-Flops, Muxes, Carry-chains, etc), and
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organizes them in clusters, each one belonging to a physical tile of the device.
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The PnR tool makes the best possible decision, based on the FPGA routing
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resources and timings between different points in the chip.</p>
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</section>
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<section id="placing">
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<h2 id="placing">Placing<a class="headerlink" href="#placing" title="Link to this heading">¶</a></h2>
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<p>After having clustered all the various primitives into the physical tiles of the
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device, the tool begins the placement process. This step consists in assigning a
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physical location to every cluster generated in the packing stage. The choice of
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the locations is based on the chosen algorithm and on the user’s parameters, but
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generally, the final goal is to find the best placement that allows the routing
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step to find more optimal solutions.</p>
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</section>
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<section id="routing">
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<h2 id="routing">Routing<a class="headerlink" href="#routing" title="Link to this heading">¶</a></h2>
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<p>Routing is one of the most demanding tasks of the whole process.
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All possible connections between the placed blocks and the information on
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the signals propagation timings, form a complex graph.
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The tool tries to find the optimal path connecting all the placed
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clusters using the information provided in the routing graph. Once all the nets
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have been routed, an output file containing the implemented design is produced.</p>
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</section>
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<section id="analysis">
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<h2 id="analysis">Analysis<a class="headerlink" href="#analysis" title="Link to this heading">¶</a></h2>
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<p>This last step usually checks the whole design in terms of timings and power
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consumption.</p>
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</section>
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</section>
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</article>
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© Copyright F4PGA Authors, 2019 - 2022.
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</div>
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Created using
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2024-10-15 12:15:18 -04:00
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<a href="http://www.sphinx-doc.org/">Sphinx</a> 8.1.3.
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2024-07-17 20:17:53 -04:00
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and
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<a href="https://github.com/f4pga/sphinx_f4pga_theme">Material for
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Sphinx</a>
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