42 lines
1.1 KiB
VHDL
42 lines
1.1 KiB
VHDL
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-- Copyright (C) 2020-2022 F4PGA Authors.
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- https://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-- SPDX-License-Identifier: Apache-2.0
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library ieee;
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context ieee.ieee_std_context;
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entity Arty_Counter is
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port (
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CLK : in std_logic;
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LEDs : out std_logic_vector(3 downto 0)
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);
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end;
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architecture arch of Arty_Counter is
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constant LOG2DELAY : natural := 22;
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signal counter : unsigned(LEDs'length+LOG2DELAY-1 downto 0) := (others=>'0');
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begin
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process (CLK) begin
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counter <= counter + 1 when rising_edge(CLK);
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end process;
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LEDs <= std_logic_vector(resize(shift_right(counter, LOG2DELAY), LEDs'length));
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end;
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