137 lines
4.1 KiB
ReStructuredText
137 lines
4.1 KiB
ReStructuredText
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Yosys
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=====
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Yosys is a Free and Open Source Verilog HDL synthesis tool. It was designed
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to be highly extensible and multiplatform. In SymbiFlow toolchain,
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it is responsible for the whole synthesis process described in `FPGA Design Flow
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<./design-flow.html>`_
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It is not necessary to call Yosys directly using the SymbiFlow
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toolchain. Nevertheless, the following description, should provide
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sufficient introduction to Yosys usage inside the project.
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It is also a good starting point for a deeper understanding of the whole
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Toolchain.
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Short description
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-----------------
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Yosys consists of several subsystems. Most distinguishable are the
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first and last one used in the synthesis process, called respectively
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*frontend* and *backend*. Intermediate subsystems are called *passes*.
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The *frontend* is responsible for changing the Verilog input file into
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internal Yosys, representation which is common for all *passes* used
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by the program. The *passes* are responsible for variety of optimizations
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(``opt_``) and simplifications (``proc_``).
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Two *passes*, that are worth
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to mention separately are ``ABC`` and ``techmap``. The first one optimizes
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logic functions from the design and assigns obtained results into Look Up Tables
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(LUTs) of chosen width. The second mentioned *pass* - ``techmap``
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is responsible for mapping the synthesized design from Yosys internal
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blocks to that located on FPGA chip including i.e. RAM, DSP and LUTs.
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Recommended synthesis flows for different FPGAs are combined into
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macros i.e. ``synth_ice40`` (for Lattice iCE40 FPGA) or ``synth_xilinx``
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(for Xilinx 7-series FPGAs).
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The *backend* on the other hand, is responsible
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for converting internal Yosys representation into one of the standardized
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formats. Symbiflow uses ``.eblif`` as its output file format.
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Usage in Toolchain
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------------------
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All operations performed by Yosys are written in ``.tcl`` script. Commands used
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in the scripts are responsible for preparing output file to match with the
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expectations of other toolchain tools.
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There is no need to change it even for big designs.
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Example of configuration script can be found below:
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.. code-block:: tcl
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yosys -import
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synth_ice40 -nocarry
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opt_expr -undriven
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opt_clean
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setundef -zero -params
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write_blif -attr -cname -param $::env(OUT_EBLIF)
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write_verilog $::env(OUT_SYNTH_V)
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It can be seen that this script perform a platform-specific process of
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synthesis, some optimization steps (``opt_`` commands), and writes the final file in
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``.eblif`` and Verilog formats. Yosys synthesis configuration scripts are platform-specific
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and can by found in ``<platform-dir>/yosys/synth.tcl``
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in `Symbiflow Architecture Definitions <https://github.com/SymbiFlow/symbiflow-arch-defs>`_
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repository.
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To understand performed operations it is worth to look at log file. Usually it
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is generated in the project build directory. It should be named ``top.eblif.log``.
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Output analysis
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---------------
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Input file:
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.. code-block:: verilog
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module top (
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input clk,
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output LD7,
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);
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localparam BITS = 1;
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localparam LOG2DELAY = 25;
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reg [BITS+LOG2DELAY-1:0] counter = 0;
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always @(posedge clk) begin
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counter <= counter + 1;
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end
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assign {LD7} = counter >> LOG2DELAY;
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endmodule
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after synthesis is described only with use of primitives appropriate for
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chosen platform:
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.. code-block:: verilog
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module top(clk, LD7);
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wire [25:0] _000_;
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wire _001_;
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...
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FDRE_ZINI #(
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.IS_C_INVERTED(1'h0),
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.ZINI(1'h1)
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) _073_ (
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.C(clk),
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.CE(_012_),
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.D(_000_[0]),
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.Q(counter[0]),
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.R(_013_)
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);
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...
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SR_GND _150_ (
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.GND(_062_)
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);
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assign _003_[25:0] = _000_;
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assign counter[25] = LD7;
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endmodule
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The same structure is described by the ``.eblif`` file.
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More information
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----------------
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Additional information about Yosys can be found on the `Yosys Project Website
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<http://www.clifford.at/yosys/>`_ , or in `Yosys Manual
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<http://www.clifford.at/yosys/files/yosys_manual.pdf>`_. You can also compile
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one of the tests described in Getting Started section and watch the log file
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to understand which operations are performed by Yosys.
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