mirror of
https://github.com/chipsalliance/f4pga.git
synced 2025-01-03 03:43:37 -05:00
91 lines
2.7 KiB
Python
91 lines
2.7 KiB
Python
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#!/usr/bin/python3
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# Symbiflow Stage Module
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# ----------------------------------------------------------------------------- #
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import os
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from sf_common import *
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from sf_module import *
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# ----------------------------------------------------------------------------- #
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def concat_fasm(fasm: str, fasm_extra: str, output: str):
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fasm_data = None
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fasm_extra_data = None
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with open(fasm, 'r') as fasm_file, open(fasm_extra, 'r') as fasm_extra_file:
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fasm_data = fasm_file.read()
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fasm_extra_data = fasm_extra_file.read()
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data = fasm_data + '\n' + fasm_extra_data
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with open(output, 'w') as output_file:
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output_file.write(data)
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def fasm_output_path(build_dir: str, top: str):
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return f'{build_dir}/{top}.fasm'
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class FasmModule(Module):
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def map_io(self, ctx: ModuleContext):
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build_dir = os.path.dirname(ctx.takes.eblif)
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return {
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'fasm': fasm_output_path(build_dir, ctx.values.top)
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}
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def execute(self, ctx: ModuleContext):
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build_dir = os.path.dirname(ctx.takes.eblif)
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vprargs = VprArgs(ctx.share, ctx.takes.eblif, ctx.values)
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optional = []
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if ctx.values.pnr_corner is not None:
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optional += ['--pnr_corner', ctx.values.pnr_corner]
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if ctx.takes.sdc:
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optional += ['--sdc', ctx.takes.sdc]
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s = ['genfasm', vprargs.arch_def,
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os.path.realpath(ctx.takes.eblif),
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'--device', vprargs.device_name,
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'--read_rr_graph', vprargs.rr_graph
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] + vprargs.optional
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if get_verbosity_level() >= 2:
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yield 'Generating FASM...\n ' + ' '.join(s)
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else:
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yield 'Generating FASM...'
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sub(*s, cwd=build_dir)
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default_fasm_output_name = fasm_output_path(build_dir, ctx.values.top)
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if default_fasm_output_name != ctx.outputs.fasm:
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shutil.move(default_fasm_output_name, ctx.outputs.fasm)
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if ctx.takes.fasm_extra:
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yield 'Appending extra FASM...'
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concat_fasm(ctx.outputs.fasm, ctx.takes.fasm_extra, ctx.outputs.fasm)
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else:
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yield 'No extra FASM to append'
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def __init__(self, _):
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self.name = 'fasm'
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self.no_of_phases = 2
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self.takes = [
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'eblif',
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'net',
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'place',
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'route',
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'fasm_extra?',
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'sdc?'
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]
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self.produces = [ 'fasm' ]
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self.values = [
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'device',
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'top',
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'pnr_corner?'
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] + vpr_specific_values()
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self.prod_meta = {
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'fasm': 'FPGA assembly file'
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}
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ModuleClass = FasmModule
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