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https://github.com/chipsalliance/f4pga.git
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58 lines
1.5 KiB
Python
58 lines
1.5 KiB
Python
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#!/usr/bin/python3
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# Symbiflow Stage Module
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# ----------------------------------------------------------------------------- #
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import os
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import shutil
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from sf_common import *
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from sf_module import *
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# ----------------------------------------------------------------------------- #
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def route_place_file(eblif: str):
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return file_noext(eblif) + '.route'
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class RouteModule(Module):
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def map_io(self, ctx: ModuleContext):
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return {
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'route': route_place_file(ctx.takes.eblif)
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}
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def execute(self, ctx: ModuleContext):
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build_dir = os.path.dirname(ctx.takes.eblif)
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vpr_options = []
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if ctx.values.vpr_options:
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vpr_options = options_dict_to_list(ctx.values.vpr_options)
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vprargs = VprArgs(ctx.share, ctx.takes.eblif, ctx.values,
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sdc_file=ctx.takes.sdc)
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yield 'Routing with VPR...'
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vpr('route', vprargs, cwd=build_dir)
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if ctx.is_output_explicit('route'):
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shutil.move(route_place_file(ctx.takes.eblif), ctx.outputs.route)
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yield 'Saving log...'
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save_vpr_log('route.log', build_dir=build_dir)
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def __init__(self, _):
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self.name = 'route'
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self.no_of_phases = 2
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self.takes = [
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'eblif',
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'place',
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'sdc?'
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]
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self.produces = [ 'route' ]
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self.values = [
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'device',
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'vpr_options?'
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] + vpr_specific_values()
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ModuleClass = RouteModule
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