102 lines
3.1 KiB
Plaintext
102 lines
3.1 KiB
Plaintext
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FOSS Flows For FPGA
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###################
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`F4PGA ➚ <https://f4pga.org/>`__, which is a Workgroup under the `CHIPS Alliance ➚ <https://chipsalliance.org>`__, is an
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Open Source solution for Hardware Description Language (HDL) to Bitstream FPGA synthesis, currently targeting
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Xilinx's 7-Series, QuickLogic's EOS-S3, and Lattice' iCE40 and ECP5 devices.
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Think of it as the GCC of FPGAs.
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The project aims to design tools that are highly extendable and multiplatform.
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.. image:: _static/images/hero.svg
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:align: center
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The elements of the project include (but are not limited to):
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* The F4PGA open source FPGA toolchains for programming FPGAs (formerly known as :gh:`SymbiFlow ➚ <https://github.com/SymbiFlow>`):
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* :gh:`F4PGA Python CLI ➚ <chipsalliance/f4pga/tree/main/f4pga>`
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* :gh:`F4PGA Architecture Definitions ➚ <SymbiFlow/f4pga-arch-defs>`
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* :gh:`F4PGA Examples ➚ <chipsalliance/f4pga-examples>`
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* :gh:`F4PGA Yosys plugins ➚ <chipsalliance/yosys-f4pga-plugins>`
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* The FPGA interchange format (an interchange format defined by CHIPS Alliance to enable interoperability between
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different FPGA tools) adopted by the F4PGA toolchain:
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* :gh:`FPGA Interchange schema ➚ <chipsalliance/fpga-interchange-schema>`
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* :gh:`FPGA Interchange Python utilities ➚ <chipsalliance/python-fpga-interchange>`
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* :gh:`FPGA Interchange Test suite ➚ <SymbiFlow/fpga-interchange-tests>`
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* The :gh:`FPGA tool performance framework ➚ <chipsalliance/fpga-tool-perf>` framework for benchmarking
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designs against various FPGA tools, and vice versa, over time.
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* FPGA visualisation tools for visual exploration of FPGA bitstream and databases:
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* :gh:`F4PGA bitstream viewer ➚ <SymbiFlow/f4pga-bitstream-viewer>`
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* :gh:`F4PGA database visualizer ➚ <chipsalliance/f4pga-database-visualizer>`
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* Other utilities (FPGA assembly format, documentation and other):
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* :gh:`F4PGA Assembly (FASM) ➚ <chipsalliance/fasm>`
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* :gh:`Xilinx bitstream generation library ➚ <SymbiFlow/f4pga-xc-fasm>`
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* :gh:`Verilog-to-routing XML utilities ➚ <SymbiFlow/vtr-xml-utils>`
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* :gh:`SDF format utilities ➚ <chipsalliance/python-sdf-timing>`
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* :gh:`F4PGA tools data manager ➚ <SymbiFlow/symbiflow-tools-data-manager>`
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* :gh:`F4PGA Sphinx Theme ➚ <SymbiFlow/sphinx_symbiflow_theme>`
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* :gh:`F4PGA Sphinx HDL diagrams ➚ <SymbiFlow/sphinxcontrib-hdl-diagrams>`
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* :gh:`F4PGA Sphinx Verilog domain ➚ <SymbiFlow/sphinx-verilog-domain>`
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Table of Contents
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=================
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.. toctree::
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:caption: About F4PGA
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getting-started
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how
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status
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community
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.. toctree::
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:caption: Python utils
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:maxdepth: 2
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f4pga/index
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f4pga/Usage
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f4pga/modules/index
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f4pga/DevNotes
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f4pga/Deprecated
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.. toctree::
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:caption: Development
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development/changes
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development/building-docs
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development/venv
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.. toctree::
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:caption: Design Flows
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flows/index
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flows/synthesis
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flows/pnr
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flows/bitstream
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flows/f4pga
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.. toctree::
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:caption: Specifications
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FPGA Assembly (FASM) ➚ <https://fasm.readthedocs.io/en/latest/>
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FPGA Interchange schema ➚ <https://chipsalliance/fpga-interchange-schema>
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.. toctree::
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:caption: Appendix
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glossary
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references
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