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<h1 id="how--page-root">How it works<a class="headerlink" href="#how--page-root" title="Link to this heading"></a></h1>
<p>To understand how F4PGA works, it is best to start with an overview of the general EDA tooling ecosystem and then
proceed to see what the F4PGA project consists of.
For both ASIC- and FPGA-oriented EDA tooling, there are three major areas that the workflows need to cover: description,
frontend and backend.</p>
<img alt="_images/EDA.svg" class="align-center" src="_images/EDA.svg"/>
<p>Hardware description languages are either established (such as Verilog and <a class="reference external" href="https://IEEE-P1076.gitlab.io/">VHDL ➚</a>) or
emerging software-inspired paradigms like
<a class="reference external" href="https://chisel.eecs.berkeley.edu/">Chisel ➚</a>,
<a class="reference external" href="https://spinalhdl.github.io/SpinalDoc-RTD/">SpinalHDL ➚</a>,
<a class="reference external" href="https://m-labs.hk/gateware/migen/">Migen ➚</a>, or
<a class="extlink-gh reference external" href="https://github.com/amaranth-lang">Amaranth ➚</a>.
Since early 2000s, free and open source tools allow simulating HDLs.
However, for several decades the major problem lay in the frontend and backend, where there was no established
standard vendor-neutral tooling that would cover all the necessary components for an end-to-end flow.
This pertains both to ASIC and FPGA workflows.
Although F4PGA focuses on the latter, some parts of F4PGA will also be useful in the former.</p>
<p>To achieve F4PGA’s goal of a complete FOSS FPGA toolchain, a number of tools and projects are necessary to provide all
the needed components of an end-to-end flow.
The F4PGA toolchains consist of logic synthesis and implementation tools, as well as chip documentation projects for
chips of various vendors.
Thus, F4PGA serves as an umbrella project for several activities.</p>
<img alt="_images/parts.svg" class="align-center" src="_images/parts.svg"/>
<p>The central resources are the so-called FPGA “architecture definitions” (i.e. documentation of how specific FPGAs work
internally) and the “interchange schema” (for logical and physical netlists).
Those definitions serve as input to frontend and backend tools, such as
<a class="reference external" href="https://yosyshq.net/yosys/">Yosys ➚</a>,
<a class="extlink-gh reference external" href="https://github.com/YosysHQ/nextpnr">nextpnr ➚</a> and <a class="reference external" href="https://verilogtorouting.org/">Verilog to Routing ➚</a>.
They are created within separate collaborating projects targeting different FPGAs:</p>
<ul class="simple">
<li><p><a class="reference external" href="https://f4pga.readthedocs.io/projects/prjxray/en/latest/index.html" title="(in Project X-Ray v0.0-3807-g72e6371b)"><span class="xref std std-doc">Project X-Ray ➚</span></a> for Xilinx 7-Series</p></li>
<li><p><a class="reference external" href="http://bygone.clairexen.net/icestorm/">Project IceStorm ➚</a> for Lattice iCE40</p></li>
<li><p><a class="reference external" href="https://prjtrellis.readthedocs.io/en/latest/index.html" title="(in Project Trellis)"><span class="xref std std-doc">Project Trellis ➚</span></a> for Lattice ECP5 FPGAs</p></li>
</ul>
<p>More information can be found at <a class="reference external" href="https://f4pga.readthedocs.io/projects/arch-defs/en/latest/index.html" title="(in F4PGA Architecture Definitions vlatest)"><span class="xref std std-doc">F4PGA Architecture Definitions ➚</span></a> and <a class="reference external" href="https://fpga-interchange-schema.readthedocs.io/index.html" title="(in FPGA Interchange Format v0.0-99-gc985b46)"><span class="xref std std-doc">FPGA Interchange ➚</span></a>.</p>
<p>To prepare a working bitstream for a particular FPGA chip, the toolchain goes through the following stages:</p>
<ul>
<li><p>A description of the FPGA chip is created with the information from the relevant bitstream documentation
project.
This part is done within the <a class="extlink-gh reference external" href="https://github.com/f4pga/f4pga-arch-defs">F4PGA Architecture Definitions ➚</a>.
The project prepares information about the timings and resources available in the chip needed at the implementation
stage, as well as techmaps for the synthesis tools.</p>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>This stage is typically pre-built and installed as assets.
However, developers contributing to the bitstream documentation might build it.</p>
</div>
</li>
<li><p>Then, logic synthesis is carried out in the <a class="reference external" href="https://yosyshq.net/yosys/">Yosys ➚</a> framework, which expresses the
user-provided hardware description by means of the block and connection types available in the chosen chip.</p></li>
<li><p>The next step is implementation.
Placement and routing tools put individual blocks from the synthesis description in specific chip locations and create
paths between them.
To do that, F4PGA uses either <a class="extlink-gh reference external" href="https://github.com/YosysHQ/nextpnr">nextpnr ➚</a> or <a class="extlink-gh reference external" href="https://github.com/verilog-to-routing/vtr-verilog-to-routing">Verilog to Routing ➚</a>.</p></li>
<li><p>Finally, the design properties are translated into a set of features available in the given FPGA chip.
These features are saved in the <a class="extlink-gh reference external" href="https://github.com/chipsalliance/fasm">FASM format ➚</a>, which is developed as part of F4PGA.
The FASM file is then translated to a bitstream, using the information from the bitstream documentation projects.</p></li>
</ul>
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