f4pga: merge platform flow definitions into a single file

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral 2022-08-15 04:10:57 +02:00
parent 6c6bb68841
commit 125245ab08
9 changed files with 1103 additions and 1157 deletions

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@ -619,16 +619,14 @@ def make_flow_config(project_flow_cfg: ProjectFlowConfig, part_name: str) -> Flo
scan_modules(str(ROOT))
platform_path = ROOT / f'platforms/{platform}.yml'
if not platform_path.exists():
raise F4PGAException(
message=f'The platform flow definition file {platform_path} for the platform ' \
f'{platform} cannot be found.'
)
with platform_path.open('r') as rfptr:
with (ROOT / 'platforms.yml').open('r') as rfptr:
platforms = yaml_load(rfptr, yaml_loader)
if platform not in platforms:
raise F4PGAException(message=f'Flow definition for platform <{platform}> cannot be found!')
flow_cfg = FlowConfig(
project_flow_cfg,
FlowDefinition(yaml_load(rfptr, yaml_loader), r_env),
FlowDefinition(platforms[platform], r_env),
part_name
)

1093
f4pga/platforms.yml Normal file

File diff suppressed because it is too large Load Diff

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@ -1,408 +0,0 @@
# Copyright (C) 2022 F4PGA Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
values:
device: ql-eos-s3
device_alt: ql-eos-s3_wlcsp
pinmap: '${shareDir}/arch/ql-eos-s3_wlcsp/pinmap_${package}.csv'
arch_def: '${shareDir}/arch/ql-eos-s3_wlcsp/arch.timing.xml'
rr_graph_lookahead_bin: '${shareDir}/arch/ql-eos-s3_wlcsp/rr_graph_ql-eos-s3_wlcsp.lookahead.bin'
rr_graph_real_bin: '${shareDir}/arch/ql-eos-s3_wlcsp/rr_graph_ql-eos-s3_wlcsp.rr_graph.real.bin'
vpr_place_delay: '${shareDir}/arch/ql-eos-s3_wlcsp/rr_graph_ql-eos-s3_wlcsp.place_delay.bin'
vpr_grid_layout_name: ql-eos-s3
vpr_options:
max_router_iterations: 500
routing_failure_predictor: 'off'
router_high_fanout_threshold: -1
constant_net_method: route
route_chan_width: 100
clock_modeling: route
place_delay_model: delta_override
router_lookahead: extended_map
check_route: quick
strict_checks: 'off'
allow_dangling_combinational_nodes: 'on'
disable_errors: 'check_unbuffered_edges:check_route'
congested_routing_iteration_threshold: '0.8'
incremental_reroute_delay_ripup: 'off'
base_cost_type: delay_normalized_length_bounded
bb_factor: '10'
initial_pres_fac: '4.0'
check_rr_graph: 'off'
pack_high_fanout_threshold: 'PB-lOGIC:18'
suppress_warnings: >-
${noisyWarnings},sum_pin_class:check_unbuffered_edges:load_rr_indexed_data_T_values:check_rr_node:trans_per_R:check_route:set_rr_graph_tool_comment
stages:
mk_build_dir:
module: 'common:mkdirs'
params:
build_dir: 'build/${device}'
synth:
module: 'common:synth'
params:
takes:
- pcf?
produces:
- synth_v
values:
tcl_scripts: '${shareDir}/scripts/pp3'
read_verilog_args: []
yosys_tcl_env:
OUT_JSON: '${:json}'
OUT_SYNTH_V: '${:synth_v}'
OUT_EBLIF: '${:eblif}'
OUT_FASM_EXTRA: '${:fasm_extra}'
TECHMAP_PATH: '${shareDir}/techmaps/pp3'
DEVICE_CELLS_SIM: '${shareDir}/arch/ql-eos-s3_wlcsp/cells/ram_sim.v'
DEVICE_CELLS_MAP: '${shareDir}/arch/ql-eos-s3_wlcsp/cells/ram_map.v'
PINMAP_FILE: '${shareDir}/arch/ql-eos-s3_wlcsp/pinmap_${package}.csv'
PCF_FILE: '${:pcf}'
PYTHON3: '${python3}'
UTILS_PATH: '${shareDir}/scripts'
prepare_sdc:
module: 'common:generic_script_wrapper'
params:
stage_name: prepare_sdc
interpreter: '${python3}'
script: '${shareDir}/scripts/process_sdc_constraints.py'
outputs:
sdc:
mode: file
file: '${:eblif[noext]}.sdc'
target: '${:eblif[noext]}.sdc'
inputs:
eblif: '${:eblif}'
sdc-in: '${:sdc-in}'
sdc-out: '${:eblif[noext]}.sdc'
pcf: '${:pcf}'
pin-map: ''
$PYTHONPATH: '${shareDir}/scripts/'
pack:
module: 'common:pack'
values:
device: ql-eos-s3
device_alt: ql-eos-s3_wlcsp
pinmap: '${shareDir}/arch/ql-eos-s3_wlcsp/pinmap_${package}.csv'
arch_def: '${shareDir}/arch/ql-eos-s3_wlcsp/arch.timing.xml'
rr_graph_lookahead_bin: '${shareDir}/arch/ql-eos-s3_wlcsp/rr_graph_ql-eos-s3_wlcsp.lookahead.bin'
rr_graph_real_bin: >-
${shareDir}/arch/ql-eos-s3_wlcsp/rr_graph_ql-eos-s3_wlcsp.rr_graph.real.bin
vpr_place_delay: >-
${shareDir}/arch/ql-eos-s3_wlcsp/rr_graph_ql-eos-s3_wlcsp.place_delay.bin
vpr_grid_layout_name: ql-eos-s3
vpr_options:
write_block_usage: block_usage.json
max_router_iterations: 500
routing_failure_predictor: 'off'
router_high_fanout_threshold: -1
constant_net_method: route
route_chan_width: 100
clock_modeling: route
place_delay_model: delta_override
router_lookahead: extended_map
check_route: quick
strict_checks: 'off'
allow_dangling_combinational_nodes: 'on'
disable_errors: 'check_unbuffered_edges:check_route'
congested_routing_iteration_threshold: '0.8'
incremental_reroute_delay_ripup: 'off'
base_cost_type: delay_normalized_length_bounded
bb_factor: '10'
initial_pres_fac: '4.0'
check_rr_graph: 'off'
pack_high_fanout_threshold: 'PB-lOGIC:18'
suppress_warnings: >-
${noisyWarnings},sum_pin_class:check_unbuffered_edges:load_rr_indexed_data_T_values:check_rr_node:trans_per_R:check_route:set_rr_graph_tool_comment
ioplace:
module: 'common:generic_script_wrapper'
params:
stage_name: ioplace
interpreter: '${python3}'
script: '${shareDir}/scripts/pp3_create_ioplace.py'
outputs:
io_place:
mode: stdout
target: '${:eblif[noext]}.ioplace'
inputs:
blif: '${:eblif}'
net: '${:net}'
pcf: '${:pcf}'
map: '${shareDir}/arch/ql-eos-s3_wlcsp/pinmap_${package}.csv'
$PYTHONPATH: '${shareDir}/scripts/'
place_constraints:
module: 'common:generic_script_wrapper'
params:
stage_name: place_constraints
interpreter: '${python3}'
script: '${shareDir}/scripts/pp3_create_place_constraints.py'
outputs:
place_constraints:
mode: stdout
target: '${:eblif[noext]}_constraints.place'
inputs:
blif: '${:eblif}'
map: '${shareDir}/arch/ql-eos-s3_wlcsp/clkmap_${package}.csv'
i: '${:io_place}'
$PYTHONPATH: '${shareDir}/scripts/'
place:
module: 'common:place'
iomux_jlink:
module: 'common:generic_script_wrapper'
params:
stage_name: iomux_jlink
interpreter: '${python3}'
script: '${shareDir}/scripts/pp3_eos_s3_iomux_config.py'
outputs:
iomux_jlink:
mode: stdout
target: '${:eblif[noext]}_iomux.jlink'
inputs:
eblif: '${:eblif}'
pcf: '${:pcf}'
map: '${shareDir}/arch/ql-eos-s3_wlcsp/pinmap_${package}.csv'
output-format: jlink
$PYTHONPATH: '${shareDir}/scripts/'
iomux_openocd:
module: 'common:generic_script_wrapper'
params:
stage_name: iomux_openocd
interpreter: '${python3}'
script: '${shareDir}/scripts/pp3_eos_s3_iomux_config.py'
outputs:
iomux_openocd:
mode: stdout
target: '${:eblif[noext]}_iomux.openocd'
inputs:
eblif: '${:eblif}'
pcf: '${:pcf}'
map: '${shareDir}/arch/ql-eos-s3_wlcsp/pinmap_${package}.csv'
output-format: openocd
$PYTHONPATH: '${shareDir}/scripts/'
iomux_binary:
module: 'common:generic_script_wrapper'
params:
stage_name: iomux_binary
interpreter: '${python3}'
script: '${shareDir}/scripts/pp3_eos_s3_iomux_config.py'
outputs:
iomux_binary:
mode: stdout
target: '${:eblif[noext]}_iomux.bin'
inputs:
eblif: '${:eblif}'
pcf: '${:pcf}'
map: '${shareDir}/arch/ql-eos-s3_wlcsp/pinmap_${package}.csv'
output-format: binary
$PYTHONPATH: '${shareDir}/scripts/'
route:
module: 'common:route'
values:
device: ql-eos-s3
device_alt: ql-eos-s3_wlcsp
pinmap: '${shareDir}/arch/ql-eos-s3_wlcsp/pinmap_${package}.csv'
arch_def: '${shareDir}/arch/ql-eos-s3_wlcsp/arch.timing.xml'
rr_graph_lookahead_bin: '${shareDir}/arch/ql-eos-s3_wlcsp/rr_graph_ql-eos-s3_wlcsp.lookahead.bin'
rr_graph_real_bin: >-
${shareDir}/arch/ql-eos-s3_wlcsp/rr_graph_ql-eos-s3_wlcsp.rr_graph.real.bin
vpr_place_delay: >-
${shareDir}/arch/ql-eos-s3_wlcsp/rr_graph_ql-eos-s3_wlcsp.place_delay.bin
vpr_grid_layout_name: ql-eos-s3
vpr_options:
write_timing_summary: timing_summary.json
max_router_iterations: 500
routing_failure_predictor: 'off'
router_high_fanout_threshold: -1
constant_net_method: route
route_chan_width: 100
clock_modeling: route
place_delay_model: delta_override
router_lookahead: extended_map
check_route: quick
strict_checks: 'off'
allow_dangling_combinational_nodes: 'on'
disable_errors: 'check_unbuffered_edges:check_route'
congested_routing_iteration_threshold: '0.8'
incremental_reroute_delay_ripup: 'off'
base_cost_type: delay_normalized_length_bounded
bb_factor: '10'
initial_pres_fac: '4.0'
check_rr_graph: 'off'
pack_high_fanout_threshold: 'PB-lOGIC:18'
suppress_warnings: >-
${noisyWarnings},sum_pin_class:check_unbuffered_edges:load_rr_indexed_data_T_values:check_rr_node:trans_per_R:check_route:set_rr_graph_tool_comment
analysis:
module: 'common:analysis'
values:
device: ql-eos-s3
device_alt: ql-eos-s3_wlcsp
pinmap: '${shareDir}/arch/ql-eos-s3_wlcsp/pinmap_${package}.csv'
arch_def: '${shareDir}/arch/ql-eos-s3_wlcsp/arch.timing.xml'
rr_graph_lookahead_bin: '${shareDir}/arch/ql-eos-s3_wlcsp/rr_graph_ql-eos-s3_wlcsp.lookahead.bin'
rr_graph_real_bin: >-
${shareDir}/arch/ql-eos-s3_wlcsp/rr_graph_ql-eos-s3_wlcsp.rr_graph.real.bin
vpr_place_delay: >-
${shareDir}/arch/ql-eos-s3_wlcsp/rr_graph_ql-eos-s3_wlcsp.place_delay.bin
vpr_grid_layout_name: ql-eos-s3
vpr_options:
gen_post_synthesis_netlist: 'on'
gen_post_implementation_merged_netlist: 'on'
post_synth_netlist_unconn_inputs: nets
post_synth_netlist_unconn_outputs: nets
verify_file_digests: 'off'
max_router_iterations: 500
routing_failure_predictor: 'off'
router_high_fanout_threshold: -1
constant_net_method: route
route_chan_width: 100
clock_modeling: route
place_delay_model: delta_override
router_lookahead: extended_map
check_route: quick
strict_checks: 'off'
allow_dangling_combinational_nodes: 'on'
disable_errors: 'check_unbuffered_edges:check_route'
congested_routing_iteration_threshold: '0.8'
incremental_reroute_delay_ripup: 'off'
base_cost_type: delay_normalized_length_bounded
bb_factor: '10'
initial_pres_fac: '4.0'
check_rr_graph: 'off'
pack_high_fanout_threshold: 'PB-lOGIC:18'
suppress_warnings: >-
${noisyWarnings},sum_pin_class:check_unbuffered_edges:load_rr_indexed_data_T_values:check_rr_node:trans_per_R:check_route:set_rr_graph_tool_comment
fasm:
module: 'common:fasm'
bitstream:
module: 'common:generic_script_wrapper'
params:
stage_name: bitstream
script: qlfasm
outputs:
bitstream:
mode: file
file: '${:eblif[noext]}.bit'
target: '${:eblif[noext]}.bit'
bitstream_log:
mode: stdout
target: '${:eblif[noext]}.bit.log'
inputs:
'#1': '${:fasm}'
'#2': '${:eblif[noext]}.bit'
dev-type: ql-eos-s3
values:
build_dir: .
bitstream_bitheader:
module: 'common:generic_script_wrapper'
params:
stage_name: bitstream_bitheader
script: symbiflow_write_bitheader
outputs:
bitstream_bitheader:
mode: file
file: '${:bitstream}.h'
target: '${:bitstream}.h'
bitstream_bitheader_log:
mode: stdout
target: '${:bitstream}.h.log'
inputs:
'#1': '${:bitstream}'
'#2': '${:bitstream}.h'
'#3': '${:iomux_binary}'
bitstream_jlink:
module: 'common:generic_script_wrapper'
params:
stage_name: bitstream_jlink
script: symbiflow_write_jlink
outputs:
bitstream_jlink:
mode: file
file: '${:bitstream}.jlink'
target: '${:bitstream}.jlink'
bitstream_jlink_log:
mode: stdout
target: '${:bitstream}.jlink.log'
inputs:
'#1': '${:bitstream}'
'#2': '${:bitstream}.jlink'
'#3': '${:iomux_jlink}'
bitstream_openocd:
module: 'common:generic_script_wrapper'
params:
stage_name: bitstream_openocd
script: symbiflow_write_openocd
outputs:
bitstream_openocd:
mode: file
file: '${:bitstream}.openocd'
target: '${:bitstream}.openocd'
bitstream_openocd_log:
mode: stdout
target: '${:bitstream}.openocd.log'
inputs:
'#1': '${:bitstream}'
'#2': '${:bitstream}.openocd'
'#3': '${:iomux_openocd}'
bitstream_binary:
module: 'common:generic_script_wrapper'
params:
stage_name: bitstream_binary
script: symbiflow_write_binary
outputs:
bitstream_binary:
mode: file
file: '${:bitstream}.bin'
target: '${:bitstream}.bin'
bitstream_binary_log:
mode: stdout
target: '${:bitstream}.bin.log'
inputs:
'#1': '${:bitstream}'
'#2': '${:bitstream}.bin'
'#3': '${:iomux_binary}'
fasm2bels:
module: 'common:generic_script_wrapper'
params:
stage_name: fasm2bels
script: symbiflow_fasm2bels
outputs:
fasm2bels_verilog:
mode: file
file: '${:bitstream}.v'
target: '${:bitstream}.v'
fasm2bels_pcf:
mode: file
file: '${:bitstream}.pcf'
target: '${:bitstream}.pcf'
fasm2bels_qcf:
mode: file
file: '${:bitstream}.qcf'
target: '${:bitstream}.qcf'
fasm2bels_log:
mode: stdout
target: '${:bitstream}.log'
inputs:
device: '${device}'
part: '${package}'
pcf: '${:pcf}'
bit: '${:bitstream}'
out-verilog: '${:bitstream}.v'
out-pcf: '${:bitstream}.pcf'
out-qcf: '${:bitstream}.qcf'
$F4PGA_INSTALL_DIR: '${shareDir}/../../../../'
$FPGA_FAM: eos-s3
$PATH: >-
${shareDir}/../../../conda/envs/eos-s3/bin/:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
$BIN_DIR_PATH: '${binDir}'

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@ -1,152 +0,0 @@
# Copyright (C) 2022 F4PGA Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
values:
device: qlf_k4n8_umc22
rr_graph_lookahead_bin: >-
${shareDir}/arch/qlf_k4n8-qlf_k4n8_umc22_fast_qlf_k4n8-qlf_k4n8_umc22_fast/rr_graph_qlf_k4n8-qlf_k4n8_umc22_fast_qlf_k4n8-qlf_k4n8_umc22_fast.lookahead.bin
rr_graph_real_bin: >-
${shareDir}/arch/qlf_k4n8-qlf_k4n8_umc22_fast_qlf_k4n8-qlf_k4n8_umc22_fast/qlf_k4n8-qlf_k4n8_umc22_fast.rr_graph.bin
vpr_place_delay: >-
${shareDir}/arch/qlf_k4n8-qlf_k4n8_umc22_fast_qlf_k4n8-qlf_k4n8_umc22_fast/rr_graph_qlf_k4n8-qlf_k4n8_umc22_fast_qlf_k4n8-qlf_k4n8_umc22_fast.place_delay.bin
vpr_grid_layout_name: qlf_k4n8-qlf_k4n8_umc22_fast
arch_def: >-
${shareDir}/arch/qlf_k4n8-qlf_k4n8_umc22_fast_qlf_k4n8-qlf_k4n8_umc22_fast/arch_qlf_k4n8-qlf_k4n8_umc22_fast_qlf_k4n8-qlf_k4n8_umc22_fast.xml
vpr_options:
max_router_iterations: 500
routing_failure_predictor: 'off'
router_high_fanout_threshold: -1
constant_net_method: route
route_chan_width: 100
clock_modeling: ideal
place_delta_delay_matrix_calculation_method: dijkstra
place_delay_model: delta_override
router_lookahead: extended_map
allow_dangling_combinational_nodes: 'on'
absorb_buffer_luts: 'off'
stages:
mk_build_dir:
module: 'common:mkdirs'
params:
build_dir: 'build/${device}'
synth:
module: 'common:synth'
params:
produces:
- synth_v
values:
tcl_scripts: '${shareDir}/scripts/qlf_k4n8'
read_verilog_args: []
yosys_tcl_env:
TOP: '${top}'
OUT_JSON: '${:json}'
TECHMAP_PATH: '${shareDir}/techmaps/qlf_k4n8'
OUT_SYNTH_V: '${:synth_v}'
OUT_EBLIF: '${:eblif}'
PYTHON3: '${python3}'
pack:
module: 'common:pack'
ioplace:
module: 'common:generic_script_wrapper'
params:
stage_name: ioplace
interpreter: '${python3}'
script: '${binDir}/python/ql_qlf_create_ioplace.py'
outputs:
io_place:
mode: stdout
target: '${:eblif[noext]}.ioplace'
inputs:
blif: '${:eblif}'
net: '${:net}'
pcf: '${:pcf}'
pinmap_xml: >-
${shareDir}/arch/qlf_k4n8-qlf_k4n8_umc22_fast_qlf_k4n8-qlf_k4n8_umc22_fast/pinmap_qlf_k4n8_umc22.xml
csv_file: >-
${shareDir}/arch/qlf_k4n8-qlf_k4n8_umc22_fast_qlf_k4n8-qlf_k4n8_umc22_fast/pinmap_qlf_k4n8_umc22.csv
$PYTHONPATH: '${binDir}/python/'
repack:
module: 'common:generic_script_wrapper'
params:
stage_name: repack
interpreter: '${python3}'
script: '${binDir}/python/repacker/repack.py'
outputs:
eblif_repacked:
mode: file
file: '${:eblif[noext]}_repacked.eblif'
target: '${:eblif[noext]}_repacked.eblif'
place_repacked:
mode: file
file: '${:place[noext]}_repacked.place'
target: '${:place[noext]}_repacked.place'
net_repacked:
mode: file
file: '${:net[noext]}_repacked.net'
target: '${:net[noext]}_repacked.net'
repack_log:
mode: stdout
target: '${top}.repack.log'
inputs:
eblif-in: '${:eblif}'
net-in: '${:net}'
place-in: '${:place}'
eblif-out: '${:eblif[noext]}_repacked.eblif'
place-out: '${:place[noext]}_repacked.place'
net-out: '${:net[noext]}_repacked.net'
absorb_buffer_luts: 'on'
vpr-arch: '${arch_def}'
repacking-rules: '${repacking_rules}'
json-constraints: '${json_constraints?}'
pcf-constraints: '${pcf?}'
$PYTHONPATH: '${binDir}/python/'
values:
repacking_rules: >-
${shareDir}/arch/qlf_k4n8-qlf_k4n8_umc22_fast_qlf_k4n8-qlf_k4n8_umc22_fast/qlf_k4n8-qlf_k4n8_umc22_fast.repacking_rules.json
place:
module: 'common:place'
route:
module: 'common:io_rename'
params:
module: 'common:route'
rename_takes:
eblif: eblif_repacked
place: place_repacked
net: net_repacked
fasm:
module: 'common:io_rename'
params:
module: 'common:fasm'
rename_takes:
eblif: eblif_repacked
place: place_repacked
net: net_repacked
bitstream:
module: 'common:generic_script_wrapper'
params:
stage_name: bitstream
script: qlf_fasm
outputs:
bitstream:
mode: file
file: '${:fasm[noext]}.bit'
target: '${:fasm[noext]}.bit'
inputs:
'#1': '${:fasm}'
'#2': '${:fasm[noext]}.bit'
db-root: '${shareDir}/fasm_database/qlf_k4n8'
format: 4byte
assemble: true

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@ -1,152 +0,0 @@
# Copyright (C) 2022 F4PGA Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
values:
device: qlf_k4n8_umc22
rr_graph_lookahead_bin: >-
${shareDir}/arch/qlf_k4n8-qlf_k4n8_umc22_slow_qlf_k4n8-qlf_k4n8_umc22_slow/rr_graph_qlf_k4n8-qlf_k4n8_umc22_slow_qlf_k4n8-qlf_k4n8_umc22_slow.lookahead.bin
rr_graph_real_bin: >-
${shareDir}/arch/qlf_k4n8-qlf_k4n8_umc22_slow_qlf_k4n8-qlf_k4n8_umc22_slow/qlf_k4n8-qlf_k4n8_umc22_slow.rr_graph.bin
vpr_place_delay: >-
${shareDir}/arch/qlf_k4n8-qlf_k4n8_umc22_slow_qlf_k4n8-qlf_k4n8_umc22_slow/rr_graph_qlf_k4n8-qlf_k4n8_umc22_slow_qlf_k4n8-qlf_k4n8_umc22_slow.place_delay.bin
vpr_grid_layout_name: qlf_k4n8-qlf_k4n8_umc22_slow
arch_def: >-
${shareDir}/arch/qlf_k4n8-qlf_k4n8_umc22_slow_qlf_k4n8-qlf_k4n8_umc22_slow/arch_qlf_k4n8-qlf_k4n8_umc22_slow_qlf_k4n8-qlf_k4n8_umc22_slow.xml
vpr_options:
max_router_iterations: 500
routing_failure_predictor: 'off'
router_high_fanout_threshold: -1
constant_net_method: route
route_chan_width: 100
clock_modeling: ideal
place_delta_delay_matrix_calculation_method: dijkstra
place_delay_model: delta_override
router_lookahead: extended_map
allow_dangling_combinational_nodes: 'on'
absorb_buffer_luts: 'off'
stages:
mk_build_dir:
module: 'common:mkdirs'
params:
build_dir: 'build/${device}'
synth:
common: synth
params:
produces:
- synth_v
values:
tcl_scripts: '${shareDir}/scripts/qlf_k4n8'
read_verilog_args: []
yosys_tcl_env:
TOP: '${top}'
OUT_JSON: '${:json}'
TECHMAP_PATH: '${shareDir}/techmaps/qlf_k4n8'
OUT_SYNTH_V: '${:synth_v}'
OUT_EBLIF: '${:eblif}'
PYTHON3: '${python3}'
pack:
module: 'common:pack'
ioplace:
module: 'common:generic_script_wrapper'
params:
stage_name: ioplace
interpreter: '${python3}'
script: '${binDir}/python/ql_qlf_create_ioplace.py'
outputs:
io_place:
mode: stdout
target: '${:eblif[noext]}.ioplace'
inputs:
blif: '${:eblif}'
net: '${:net}'
pcf: '${:pcf}'
pinmap_xml: >-
${shareDir}/arch/qlf_k4n8-qlf_k4n8_umc22_slow_qlf_k4n8-qlf_k4n8_umc22_slow/pinmap_qlf_k4n8_umc22.xml
csv_file: >-
${shareDir}/arch/qlf_k4n8-qlf_k4n8_umc22_slow_qlf_k4n8-qlf_k4n8_umc22_slow/pinmap_qlf_k4n8_umc22.csv
$PYTHONPATH: '${binDir}/python/'
repack:
module: 'common:generic_script_wrapper'
params:
stage_name: repack
interpreter: '${python3}'
script: '${binDir}/python/repacker/repack.py'
outputs:
eblif_repacked:
mode: file
file: '${:eblif[noext]}_repacked.eblif'
target: '${:eblif[noext]}_repacked.eblif'
place_repacked:
mode: file
file: '${:place[noext]}_repacked.place'
target: '${:place[noext]}_repacked.place'
net_repacked:
mode: file
file: '${:net[noext]}_repacked.net'
target: '${:net[noext]}_repacked.net'
repack_log:
mode: stdout
target: '${top}.repack.log'
inputs:
eblif-in: '${:eblif}'
net-in: '${:net}'
place-in: '${:place}'
eblif-out: '${:eblif[noext]}_repacked.eblif'
place-out: '${:place[noext]}_repacked.place'
net-out: '${:net[noext]}_repacked.net'
absorb_buffer_luts: 'on'
vpr-arch: '${arch_def}'
repacking-rules: '${repacking_rules}'
json-constraints: '${json_constraints?}'
pcf-constraints: '${pcf?}'
$PYTHONPATH: '${binDir}/python/'
values:
repacking_rules: >-
${shareDir}/arch/qlf_k4n8-qlf_k4n8_umc22_slow_qlf_k4n8-qlf_k4n8_umc22_slow/qlf_k4n8-qlf_k4n8_umc22_slow.repacking_rules.json
place:
module: 'common:place'
route:
module: 'common:io_rename'
params:
module: 'common:route'
rename_takes:
eblif: eblif_repacked
place: place_repacked
net: net_repacked
fasm:
module: 'common:io_rename'
params:
module: 'common:fasm'
rename_takes:
eblif: eblif_repacked
place: place_repacked
net: net_repacked
bitstream:
module: 'common:generic_script_wrapper'
params:
stage_name: bitstream
script: qlf_fasm
outputs:
bitstream:
mode: file
file: '${:fasm[noext]}.bit'
target: '${:fasm[noext]}.bit'
inputs:
'#1': '${:fasm}'
'#2': '${:fasm[noext]}.bit'
db-root: '${shareDir}/fasm_database/qlf_k4n8'
format: 4byte
assemble: true

View File

@ -1,144 +0,0 @@
# Copyright (C) 2022 F4PGA Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
values:
device: xc7a100t_test
bitstream_device: artix7
pinmap: '${shareDir}/arch/xc7a100t_test/vpr_grid_map.csv'
arch_def: '${shareDir}/arch/xc7a100t_test/arch.timing.xml'
rr_graph_lookahead_bin: '${shareDir}/arch/xc7a100t_test/rr_graph_xc7a100t_test.lookahead.bin'
rr_graph_real_bin: '${shareDir}/arch/xc7a100t_test/rr_graph_xc7a100t_test.rr_graph.real.bin'
vpr_place_delay: '${shareDir}/arch/xc7a100t_test/rr_graph_xc7a100t_test.place_delay.bin'
vpr_grid_layout_name: xc7a100t-test
vpr_options:
max_router_iterations: 500
routing_failure_predictor: 'off'
router_high_fanout_threshold: -1
constant_net_method: route
route_chan_width: 500
router_heap: bucket
clock_modeling: route
place_delta_delay_matrix_calculation_method: dijkstra
place_delay_model: delta
router_lookahead: extended_map
check_route: quick
strict_checks: 'off'
allow_dangling_combinational_nodes: 'on'
disable_errors: 'check_unbuffered_edges:check_route'
congested_routing_iteration_threshold: '0.8'
incremental_reroute_delay_ripup: 'off'
base_cost_type: delay_normalized_length_bounded
bb_factor: 10
acc_fac: '0.7'
astar_fac: '1.8'
initial_pres_fac: '2.828'
pres_fac_mult: '1.2'
check_rr_graph: 'off'
suppress_warnings: >-
${noisyWarnings},sum_pin_class:check_unbuffered_edges:load_rr_indexed_data_T_values:check_rr_node:trans_per_R:check_route:set_rr_graph_tool_comment:calculate_average_switch
stages:
mk_build_dir:
module: 'common:mkdirs'
params:
build_dir: 'build/${device}'
synth:
module: 'common:synth'
params:
takes:
- xdc?
produces:
- sdc
- synth_v
prod_meta:
sdc: Standard Design Constraints file for X7 series.
values:
tcl_scripts: '${shareDir}/scripts/xc7'
yosys_tcl_env:
USE_ROI: 'FALSE'
TOP: '${top}'
OUT_JSON: '${:json}'
OUT_SDC: '${:sdc}'
PART_JSON: '${prjxray_db}/${bitstream_device}/${part_name}/part.json'
OUT_FASM_EXTRA: '${:fasm_extra}'
TECHMAP_PATH: '${shareDir}/techmaps/xc7_vpr/techmap'
OUT_SYNTH_V: '${:synth_v}'
SYNTH_JSON: '${:synth_json}'
OUT_EBLIF: '${:eblif}'
PYTHON3: '${python3}'
UTILS_PATH: '${shareDir}/scripts'
INPUT_XDC_FILES: '${:xdc}'
pack:
module: 'common:pack'
ioplace:
module: 'common:generic_script_wrapper'
params:
stage_name: ioplace
interpreter: '${python3}'
script: '${shareDir}/scripts/prjxray_create_ioplace.py'
outputs:
io_place:
mode: stdout
target: '${:net[noext]}.ioplace'
inputs:
blif: '${:eblif}'
map: '${shareDir}/arch/${device}/${part_name}/pinmap.csv'
net: '${:net}'
pcf: '${:pcf?}'
$PYTHONPATH: '${binDir}/python/'
place_constraints:
module: 'common:generic_script_wrapper'
params:
stage_name: place_constraints
interpreter: '${python3}'
script: '${shareDir}/scripts/prjxray_create_place_constraints.py'
outputs:
place_constraints:
mode: stdout
target: '${:net[noext]}.preplace'
inputs:
net: '${:net}'
arch: '${shareDir}/arch/${device}/arch.timing.xml'
blif: '${:eblif}'
input: '${:io_place}'
db_root: '${prjxray_db}'
part: '${part_name}'
vpr_grid_map: '${shareDir}/arch/${device}/vpr_grid_map.csv'
$PYTHONPATH: '${binDir}/python/'
place:
module: 'common:place'
route:
module: 'common:route'
fasm:
module: 'common:fasm'
bitstream:
module: 'common:generic_script_wrapper'
params:
stage_name: bitstream
script: xcfasm
outputs:
bitstream:
mode: file
file: '${:fasm[noext]}.bit'
target: '${:fasm[noext]}.bit'
inputs:
db-root: '${prjxray_db}/${bitstream_device}'
part: '${part_name}'
part_file: '${prjxray_db}/${bitstream_device}/${part_name}/part.yaml'
sparse: true
emit_pudc_b_pullup: true
fn_in: '${:fasm}'
frm2bit: xc7frames2bit
bit_out: '${:fasm[noext]}.bit'

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@ -1,144 +0,0 @@
# Copyright (C) 2022 F4PGA Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
values:
device: xc7a200t_test
bitstream_device: artix7
pinmap: '${shareDir}/arch/xc7a200t_test/vpr_grid_map.csv'
arch_def: '${shareDir}/arch/xc7a200t_test/arch.timing.xml'
rr_graph_lookahead_bin: '${shareDir}/arch/xc7a200t_test/rr_graph_xc7a200t_test.lookahead.bin'
rr_graph_real_bin: '${shareDir}/arch/xc7a200t_test/rr_graph_xc7a200t_test.rr_graph.real.bin'
vpr_place_delay: '${shareDir}/arch/xc7a200t_test/rr_graph_xc7a200t_test.place_delay.bin'
vpr_grid_layout_name: xc7a200t-test
vpr_options:
max_router_iterations: 500
routing_failure_predictor: 'off'
router_high_fanout_threshold: -1
constant_net_method: route
route_chan_width: 500
router_heap: bucket
clock_modeling: route
place_delta_delay_matrix_calculation_method: dijkstra
place_delay_model: delta
router_lookahead: extended_map
check_route: quick
strict_checks: 'off'
allow_dangling_combinational_nodes: 'on'
disable_errors: 'check_unbuffered_edges:check_route'
congested_routing_iteration_threshold: '0.8'
incremental_reroute_delay_ripup: 'off'
base_cost_type: delay_normalized_length_bounded
bb_factor: 10
acc_fac: '0.7'
astar_fac: '1.8'
initial_pres_fac: '2.828'
pres_fac_mult: '1.2'
check_rr_graph: 'off'
suppress_warnings: >-
${noisyWarnings},sum_pin_class:check_unbuffered_edges:load_rr_indexed_data_T_values:check_rr_node:trans_per_R:check_route:set_rr_graph_tool_comment:calculate_average_switch
stages:
mk_build_dir:
module: 'common:mkdirs'
params:
build_dir: 'build/${device}'
synth:
module: 'common:synth'
params:
takes:
- xdc?
produces:
- sdc
- synth_v
prod_meta:
sdc: Standard Design Constraints file for X7 series.
values:
tcl_scripts: '${shareDir}/scripts/xc7'
yosys_tcl_env:
USE_ROI: 'FALSE'
TOP: '${top}'
OUT_JSON: '${:json}'
OUT_SDC: '${:sdc}'
PART_JSON: '${prjxray_db}/${bitstream_device}/${part_name}/part.json'
OUT_FASM_EXTRA: '${:fasm_extra}'
TECHMAP_PATH: '${shareDir}/techmaps/xc7_vpr/techmap'
OUT_SYNTH_V: '${:synth_v}'
SYNTH_JSON: '${:synth_json}'
OUT_EBLIF: '${:eblif}'
PYTHON3: '${python3}'
UTILS_PATH: '${shareDir}/scripts'
INPUT_XDC_FILES: '${:xdc}'
pack:
module: 'common:pack'
ioplace:
module: 'common:generic_script_wrapper'
params:
stage_name: ioplace
interpreter: '${python3}'
script: '${shareDir}/scripts/prjxray_create_ioplace.py'
outputs:
io_place:
mode: stdout
target: '${:net[noext]}.ioplace'
inputs:
blif: '${:eblif}'
map: '${shareDir}/arch/${device}/${part_name}/pinmap.csv'
net: '${:net}'
pcf: '${:pcf?}'
$PYTHONPATH: '${binDir}/python/'
place_constraints:
module: 'common:generic_script_wrapper'
params:
stage_name: place_constraints
interpreter: '${python3}'
script: '${shareDir}/scripts/prjxray_create_place_constraints.py'
outputs:
place_constraints:
mode: stdout
target: '${:net[noext]}.preplace'
inputs:
net: '${:net}'
arch: '${shareDir}/arch/${device}/arch.timing.xml'
blif: '${:eblif}'
input: '${:io_place}'
db_root: '${prjxray_db}'
part: '${part_name}'
vpr_grid_map: '${shareDir}/arch/${device}/vpr_grid_map.csv'
$PYTHONPATH: '${binDir}/python/'
place:
module: 'common:place'
route:
module: 'common:route'
fasm:
module: 'common:fasm'
bitstream:
module: 'common:generic_script_wrapper'
params:
stage_name: bitstream
script: xcfasm
outputs:
bitstream:
mode: file
file: '${:fasm[noext]}.bit'
target: '${:fasm[noext]}.bit'
inputs:
db-root: '${prjxray_db}/${bitstream_device}'
part: '${part_name}'
part_file: '${prjxray_db}/${bitstream_device}/${part_name}/part.yaml'
sparse: true
emit_pudc_b_pullup: true
fn_in: '${:fasm}'
frm2bit: xc7frames2bit
bit_out: '${:fasm[noext]}.bit'

View File

@ -1,144 +0,0 @@
# Copyright (C) 2022 F4PGA Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
values:
device: xc7a50t_test
bitstream_device: artix7
pinmap: '${shareDir}/arch/xc7a50t_test/vpr_grid_map.csv'
arch_def: '${shareDir}/arch/xc7a50t_test/arch.timing.xml'
rr_graph_lookahead_bin: '${shareDir}/arch/xc7a50t_test/rr_graph_xc7a50t_test.lookahead.bin'
rr_graph_real_bin: '${shareDir}/arch/xc7a50t_test/rr_graph_xc7a50t_test.rr_graph.real.bin'
vpr_place_delay: '${shareDir}/arch/xc7a50t_test/rr_graph_xc7a50t_test.place_delay.bin'
vpr_grid_layout_name: xc7a50t-test
vpr_options:
max_router_iterations: 500
routing_failure_predictor: 'off'
router_high_fanout_threshold: -1
constant_net_method: route
route_chan_width: 500
router_heap: bucket
clock_modeling: route
place_delta_delay_matrix_calculation_method: dijkstra
place_delay_model: delta
router_lookahead: extended_map
check_route: quick
strict_checks: 'off'
allow_dangling_combinational_nodes: 'on'
disable_errors: 'check_unbuffered_edges:check_route'
congested_routing_iteration_threshold: '0.8'
incremental_reroute_delay_ripup: 'off'
base_cost_type: delay_normalized_length_bounded
bb_factor: 10
acc_fac: '0.7'
astar_fac: '1.8'
initial_pres_fac: '2.828'
pres_fac_mult: '1.2'
check_rr_graph: 'off'
suppress_warnings: >-
${noisyWarnings},sum_pin_class:check_unbuffered_edges:load_rr_indexed_data_T_values:check_rr_node:trans_per_R:check_route:set_rr_graph_tool_comment:calculate_average_switch
stages:
mk_build_dir:
module: 'common:mkdirs'
params:
build_dir: 'build/${device}'
synth:
module: 'common:synth'
params:
takes:
- xdc?
produces:
- sdc
- synth_v
prod_meta:
sdc: Standard Design Constraints file for X7 series.
values:
tcl_scripts: '${shareDir}/scripts/xc7'
yosys_tcl_env:
USE_ROI: 'FALSE'
TOP: '${top}'
OUT_JSON: '${:json}'
OUT_SDC: '${:sdc}'
PART_JSON: '${prjxray_db}/${bitstream_device}/${part_name}/part.json'
OUT_FASM_EXTRA: '${:fasm_extra}'
TECHMAP_PATH: '${shareDir}/techmaps/xc7_vpr/techmap'
OUT_SYNTH_V: '${:synth_v}'
SYNTH_JSON: '${:synth_json}'
OUT_EBLIF: '${:eblif}'
PYTHON3: '${python3}'
UTILS_PATH: '${shareDir}/scripts'
INPUT_XDC_FILES: '${:xdc}'
pack:
module: 'common:pack'
ioplace:
module: 'common:generic_script_wrapper'
params:
stage_name: ioplace
interpreter: '${python3}'
script: '${shareDir}/scripts/prjxray_create_ioplace.py'
outputs:
io_place:
mode: stdout
target: '${:net[noext]}.ioplace'
inputs:
blif: '${:eblif}'
map: '${shareDir}/arch/${device}/${part_name}/pinmap.csv'
net: '${:net}'
pcf: '${:pcf?}'
$PYTHONPATH: '${binDir}/python/'
place_constraints:
module: 'common:generic_script_wrapper'
params:
stage_name: place_constraints
interpreter: '${python3}'
script: '${shareDir}/scripts/prjxray_create_place_constraints.py'
outputs:
place_constraints:
mode: stdout
target: '${:net[noext]}.preplace'
inputs:
net: '${:net}'
arch: '${shareDir}/arch/${device}/arch.timing.xml'
blif: '${:eblif}'
input: '${:io_place}'
db_root: '${prjxray_db}'
part: '${part_name}'
vpr_grid_map: '${shareDir}/arch/${device}/vpr_grid_map.csv'
$PYTHONPATH: '${binDir}/python/'
place:
module: 'common:place'
route:
module: 'common:route'
fasm:
module: 'common:fasm'
bitstream:
module: 'common:generic_script_wrapper'
params:
stage_name: bitstream
script: xcfasm
outputs:
bitstream:
mode: file
file: '${:fasm[noext]}.bit'
target: '${:fasm[noext]}.bit'
inputs:
db-root: '${prjxray_db}/${bitstream_device}'
part: '${part_name}'
part_file: '${prjxray_db}/${bitstream_device}/${part_name}/part.yaml'
sparse: true
emit_pudc_b_pullup: true
fn_in: '${:fasm}'
frm2bit: xc7frames2bit
bit_out: '${:fasm[noext]}.bit'

View File

@ -89,7 +89,6 @@ setuptools_setup(
package_data={
'f4pga': [
'*.yml',
'platforms/*.yml'
],
'f4pga.wrappers.sh': [
'xc7/*.f4pga.sh',