f4pga: split_inouts moved from arch-defs (#625)
This commit is contained in:
Unai Martinez-Corral
GitHub
commit
1f36d814ff
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@ -23,6 +23,7 @@ from pathlib import Path
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from f4pga.flows.common import decompose_depname, get_verbosity_level, sub as common_sub
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from f4pga.flows.module import Module, ModuleContext
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from f4pga.wrappers.tcl import get_script_path as get_tcl_wrapper_path
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from f4pga.utils import split_inouts
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class SynthModule(Module):
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@ -83,14 +84,7 @@ class SynthModule(Module):
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)
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yield f"Splitting in/outs..."
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common_sub(
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"python3",
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str(Path(tcl_env["UTILS_PATH"]) / "split_inouts.py"),
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"-i",
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ctx.outputs.json,
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"-o",
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ctx.outputs.synth_json,
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)
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split_inouts(ctx.outputs.json, ctx.outputs.synth_json)
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if not Path(ctx.produces.fasm_extra).is_file():
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with Path(ctx.produces.fasm_extra).open("w") as wfptr:
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@ -78,7 +78,6 @@ setuptools_setup(
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author="F4PGA Authors",
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description="F4PGA.",
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url="https://github.com/chipsalliance/f4pga",
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packages=["f4pga", "f4pga.flows", "f4pga.flows.common_modules", "f4pga.wrappers.sh", "f4pga.wrappers.tcl"],
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package_dir={"f4pga": "."},
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package_data={
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"f4pga.flows": [
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@ -0,0 +1,20 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2022 F4PGA Authors
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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from f4pga.utils.split_inouts import main as split_inouts
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@ -0,0 +1,278 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2019-2022 F4PGA Authors
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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"""
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This script provides a temporary solution for the problem of inout top level
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port representation of the BLIF format.
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The script loads the design from a JSON file generated by Yosys. Then it splits
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all inout ports along with their nets and connections to cell ports into two.
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Suffixes are automatically added to distinguish between the input and the
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output part.
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The JSON design format used by Yosys is documented there:
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- http://www.clifford.at/yosys/cmd_write_json.html
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- http://www.clifford.at/yosys/cmd_read_json.html
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For example in the given design (in verilog):
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module top(
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input A,
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output B,
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inout C
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);
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IOBUF iobuf (
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.I(A),
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.O(B),
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.IO_$inp(C),
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.IO_$out(C)
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);
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endmodule
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the resulting design would be:
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module top(
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input A,
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output B,
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input C_$inp,
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output C_$out
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);
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IOBUF iobuf (
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.I(A),
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.O(B),
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.IO_$inp(C_$inp),
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.IO_$out(C_$out)
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);
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endmodule
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"""
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from pathlib import Path
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from os.path import splitext
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import simplejson as json
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from argparse import ArgumentParser, RawDescriptionHelpFormatter
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def find_top_module(design):
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"""
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Looks for the top-level module in the design. Returns its name. Throws
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an exception if none was found.
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"""
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for name, module in design["modules"].items():
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attrs = module["attributes"]
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if "top" in attrs and int(attrs["top"]) == 1:
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return name
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raise RuntimeError("No top-level module found in the design!")
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def get_nets(bits):
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"""
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Returns a set of numbers corresponding to net indices effectively skipping
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connections to consts ("0", "1", "x").
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>>> get_nets([0, 1, 2, "0", "1", "x", 3, 4, 5])
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{0, 1, 2, 3, 4, 5}
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"""
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return set([n for n in bits if isinstance(n, int)])
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def get_free_net(nets):
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"""
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Given a set of used net indices, returns a new, free index.
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>>> get_free_net({0, 1, 2, 4, 5, 6})
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3
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>>> get_free_net({0, 1, 2, 3, 4, 5, 6})
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7
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"""
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sorted_nets = sorted(list(nets))
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# Find a gap in the sequence
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for i in range(len(nets) - 1):
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n0 = sorted_nets[i]
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n1 = sorted_nets[i + 1]
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if n1 != (n0 + 1):
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return n0 + 1
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# No gap was found, return max + 1.
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return sorted_nets[-1] + 1
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def main(input: str, output: str = None):
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if output is None:
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output = splitext(input)[0] + "_out.json"
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with Path(input).open("r") as fp:
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design = json.load(fp)
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module_name = find_top_module(design)
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# Take a module from the design and split all of its inout ports into pairs of inputs and outputs.
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# Newly created ports are given suffixed.
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# For example an inout port named "A" is going to be replaced by a pair consisting of "A_$inp" and "A_$out" ports.
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# The function also looks for "netnames" that correspond to inout ports being split.
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# These ones are removed and replaced with new ones related to newly added input and output ports.
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# If any other "netname" mentions a net index connected to a former inout port, then the index is removed from the
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# "netname" (replaced by "x").
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# If there are only "x" left in the "netname", then it is removed.
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# The function returns port name map and net index map.
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# The port map is a list of pairs (input name, input/output name).
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# There are two entries per an inout.
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# The net map is a dict indexed by indices of nets associated with inout ports.
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# Each item contains a dict like {"i": int, "o": int} with indices of the inout net split products.
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# Get the module
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module = design["modules"][module_name]
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# Find indices of all used nets
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nets = set()
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for port in module["ports"].values():
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nets |= get_nets(port["bits"])
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for netname in module["netnames"].values():
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nets |= get_nets(netname["bits"])
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for cell in module["cells"].values():
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for connection in cell["connections"].values():
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nets |= get_nets(connection)
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# Get all inout ports
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inouts = {k: v for k, v in module["ports"].items() if v["direction"] == "inout"}
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# Split ports
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new_ports = {}
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net_map = {}
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port_map = []
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for name, port in inouts.items():
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# Remove the inout port from the module
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del module["ports"][name]
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nets -= get_nets(port["bits"])
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# Make an input and output port
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for dir in ["input", "output"]:
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new_name = name + "_$" + dir[:3]
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new_port = {"direction": dir, "bits": []}
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print("Mapping port '{}' to '{}'".format(name, new_name))
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for n in port["bits"]:
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if isinstance(n, int):
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mapped_n = get_free_net(nets)
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print("Mapping net {} to {} ({})".format(n, mapped_n, dir))
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if n not in net_map:
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net_map[n] = {}
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net_map[n][dir[0]] = mapped_n
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nets.add(mapped_n)
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new_port["bits"].append(mapped_n)
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else:
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new_port["bits"].append(n)
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port_map.append(
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(
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name,
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new_name,
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)
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)
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new_ports[new_name] = new_port
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# Add inputs and outputs
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module["ports"].update(new_ports)
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netnames = module["netnames"]
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# Remove netnames related to inout ports
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for name, net in list(netnames.items()):
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if name in inouts:
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print(f"Removing netname '{name}'")
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del netnames[name]
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# Remove remapped nets
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for name, net in list(netnames.items()):
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# Remove "bits" used by the net that were re-mapped.
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if len(set(net["bits"]) & set(net_map.keys())):
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# Remove
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net["bits"] = ["x" if b in net_map else b for b in net["bits"]]
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# If there is nothing left, remove the whole net.
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if all([b == "x" for b in net["bits"]]):
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print(f"Removing netname '{name}'")
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del netnames[name]
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# Add netnames related to new input and output ports
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for name, port in new_ports.items():
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netnames[name] = {"hide_name": 0, "bits": port["bits"], "attributes": {}}
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# Remap cell connections that mention inout ports being split.
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# Loop over all cells and their ports.
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# If a port contains a connection to an inout net, then the connection is remapped according to the given
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# net_map.
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# Only ports which names ends on "_$inp" and "_$out" are affected.
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module = design["modules"][module_name]
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cells = module["cells"]
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# Process cells
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for name, cell in cells.items():
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if "port_directions" not in cell:
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continue
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port_directions = cell["port_directions"]
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connections = cell["connections"]
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# Process cell connections
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for port_name, port_nets in list(connections.items()):
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# Skip if no net of this connection were remapped
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if len(set(net_map.keys()) & set(port_nets)) == 0:
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continue
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# Remove connections to the output net from input port and vice
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# versa.
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for dir in ["input", "output"]:
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if port_directions[port_name] == dir and port_name.endswith("$" + dir[:3]):
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for i, n in enumerate(port_nets):
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if n in net_map:
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mapped_n = net_map[n][dir[0]]
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port_nets[i] = mapped_n
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print("Mapping connection {}.{}[{}] from {} to {}".format(name, port_name, i, n, mapped_n))
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with Path(output).open("w") as fp:
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json.dump(design, fp, sort_keys=True, indent=2)
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if __name__ == "__main__":
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parser = ArgumentParser(description=__doc__, formatter_class=RawDescriptionHelpFormatter)
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parser.add_argument("-i", required=True, type=str, help="Input JSON")
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parser.add_argument("-o", default=None, type=str, help="Output JSON")
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args = parser.parse_args()
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main(args.i, args.o)
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@ -18,7 +18,6 @@
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set -e
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SPLIT_INOUTS="${F4PGA_SHARE_DIR}"/scripts/split_inouts.py
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CONVERT_OPTS="${F4PGA_SHARE_DIR}"/scripts/convert_compile_opts.py
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print_usage () {
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@ -177,5 +176,5 @@ if [ ! -z "${YOSYS_COMMANDS}" ]; then
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fi
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`which yosys` -p "${YOSYS_SCRIPT}" -l $LOG
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`which python3` ${SPLIT_INOUTS} -i ${OUT_JSON} -o ${SYNTH_JSON}
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`which python3` -m f4pga.utils.split_inouts -i ${OUT_JSON} -o ${SYNTH_JSON}
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`which yosys` -p "read_json $SYNTH_JSON; tcl ${CONV_TCL_PATH}"
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@ -139,5 +139,5 @@ else
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yosys -p "plugin -i uhdm" -p "read_verilog_with_uhdm ${SURELOG_CMD[*]} ${VERILOG_FILES[*]}" -p "tcl ${SYNTH_TCL_PATH}" -l $LOG
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fi
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python3 ${UTILS_PATH}/split_inouts.py -i ${OUT_JSON} -o ${SYNTH_JSON}
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python3 -m f4pga.utils.split_inouts -i ${OUT_JSON} -o ${SYNTH_JSON}
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yosys -p "read_json $SYNTH_JSON; tcl $(python3 -m f4pga.wrappers.tcl conv)"
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@ -70,6 +70,8 @@ for PKG in $PACKAGES; do
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| tar -xJC $F4PGA_INSTALL_DIR_FAM
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done
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find $F4PGA_INSTALL_DIR_FAM/share -name split_inouts.py | xargs rm -v
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echo '::endgroup::'
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