f4pga/flows/common_modules/route: pass vpr_extra_options
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
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@ -34,10 +34,18 @@ class RouteModule(Module):
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def execute(self, ctx: ModuleContext):
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build_dir = Path(ctx.takes.eblif).parent
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vpr_options = options_dict_to_list(ctx.values.vpr_options) if ctx.values.vpr_options else []
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yield "Routing with VPR..."
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common_vpr("route", VprArgs(ctx.share, ctx.takes.eblif, ctx.values, sdc_file=ctx.takes.sdc), cwd=build_dir)
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common_vpr(
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"route",
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VprArgs(
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ctx.share,
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ctx.takes.eblif,
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ctx.values,
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sdc_file=ctx.takes.sdc,
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vpr_extra_opts=options_dict_to_list(ctx.values.vpr_options) if ctx.values.vpr_options else None,
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),
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cwd=build_dir,
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)
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if ctx.is_output_explicit("route"):
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route_place_file(ctx).rename(ctx.outputs.route)
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