Rename aux -> auxiliary

Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
This commit is contained in:
Krzysztof Boronski 2022-09-07 18:31:41 +02:00
parent 693312f3ea
commit 3be913535e
10 changed files with 4 additions and 4 deletions
f4pga
auxiliary/tool_data/yosys/scripts
flows
setup.py
wrappers/sh

View file

@ -30,7 +30,7 @@ from f4pga.context import FPGA_FAM, F4PGA_SHARE_DIR
bin_dir_path = str(Path(sys_argv[0]).resolve().parent.parent)
share_dir_path = str(F4PGA_SHARE_DIR)
aux_dir_path = str(Path(__file__).resolve().parent.parent / "aux")
aux_dir_path = str(Path(__file__).resolve().parent.parent / "auxiliary")
class F4PGAException(Exception):

View file

@ -80,7 +80,7 @@ setuptools_setup(
url="https://github.com/chipsalliance/f4pga",
package_dir={"f4pga": "."},
package_data={
"f4pga": ["aux/**/*.tcl"],
"f4pga": ["auxiliary/**/*.tcl"],
"f4pga.flows": ["*.yml"],
"f4pga.wrappers.sh": [
"xc7/*.f4pga.sh",

View file

@ -27,7 +27,7 @@ export SHARE_DIR_PATH=${SHARE_DIR_PATH:="$F4PGA_SHARE_DIR"}
export UTILS_PATH=${SHARE_DIR_PATH}/scripts
F4PGA_AUX_PATH=`realpath ${MYDIR}/../../../aux`
F4PGA_AUX_PATH=`realpath ${MYDIR}/../../../auxiliary`
F4PGA_EXEC_TCL_PATH=${F4PGA_AUX_PATH}/tool_data/yosys/scripts/common/f4pga_exec.tcl
F4PGA_COMMON_TCL_PATH=${F4PGA_AUX_PATH}/tool_data/yosys/scripts/common/common.tcl
SYNTH_TCL_PATH=${F4PGA_AUX_PATH}/tool_data/yosys/scripts/vendor/quicklogic/pp3/synth.tcl

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@ -23,7 +23,7 @@ MYDIR=`dirname $MYPATH`
source ${MYDIR}/../common.f4pga.sh
F4PGA_AUX_PATH=`realpath ${MYDIR}/../../../aux`
F4PGA_AUX_PATH=`realpath ${MYDIR}/../../../auxiliary`
F4PGA_EXEC_TCL_PATH=${F4PGA_AUX_PATH}/tool_data/yosys/scripts/common/f4pga_exec.tcl
F4PGA_COMMON_TCL_PATH=${F4PGA_AUX_PATH}/tool_data/yosys/scripts/common/common.tcl
SYNTH_TCL_PATH=${F4PGA_AUX_PATH}/tool_data/yosys/scripts/vendor/xilinx/xc7/synth.tcl