wrappers: ql: move utility scripts to share dir

Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>

f4pga/wrappers/sh/quicklogic/fasm2bels.f4pga.sh

@@ -71,7 +71,7 @@ fi
 if [[ "$DEVICE" =~ ^(ql-eos-s3|ql-pp3e)$ ]]; then
 
     VPR_DB=`readlink -f ${SHARE_DIR_PATH}/arch/${DEVICE}_wlcsp/db_phy.pickle`
-    FASM2BELS=`readlink -f ${BIN_DIR_PATH}/python/fasm2bels.py`
+    FASM2BELS=`readlink -f ${SHARE_DIR_PATH}/scripts/fasm2bels.py`
     FASM2BELS_DEVICE=${DEVICE/ql-/}
     VERILOG_FILE="${BIT}.v"
     PCF_FILE="${BIT}.v.pcf"

f4pga/wrappers/sh/quicklogic/generate_constraints.f4pga.sh

@@ -49,7 +49,7 @@ if [[ "$DEVICE" =~ ^(qlf_.*)$ ]]; then
   fi
 
   PINMAP_XML=`realpath ${SHARE_DIR_PATH}/arch/${DEVICE_1}_${DEVICE_1}/${PINMAPXML}`
-  IOGEN=`realpath ${BIN_DIR_PATH}/python/qlf_k4n8_create_ioplace.py`
+  IOGEN=`realpath ${SHARE_DIR_PATH}/scripts/qlf_k4n8_create_ioplace.py`
 
   ${PYTHON3} ${IOGEN} --pcf $PCF --blif $EBLIF --pinmap_xml $PINMAP_XML --csv_file $PART --net $NET > ${IOPLACE_FILE}
 
@@ -71,8 +71,8 @@ elif [[ "$DEVICE" =~ ^(ql-.*)$ ]]; then
   PINMAP=`realpath ${SHARE_DIR_PATH}/arch/${DEVICE_1}_${DEVICE_2}/${PINMAPCSV}`
   CLKMAP=`realpath ${SHARE_DIR_PATH}/arch/${DEVICE_1}_${DEVICE_2}/${CLKMAPCSV}`
 
-  IOGEN=`realpath ${BIN_DIR_PATH}/python/pp3_create_ioplace.py`
-  PLACEGEN=`realpath ${BIN_DIR_PATH}/python/pp3_create_place_constraints.py`
+  IOGEN=`realpath ${SHARE_DIR_PATH}/scripts/pp3_create_ioplace.py`
+  PLACEGEN=`realpath ${SHARE_DIR_PATH}/scripts/pp3_create_place_constraints.py`
 
   PLACE_FILE="${PROJECT%.*}_constraints.place"
 
@@ -82,7 +82,7 @@ elif [[ "$DEVICE" =~ ^(ql-.*)$ ]]; then
   # EOS-S3 IOMUX configuration
   if [[ "$DEVICE" =~ ^(ql-eos-s3)$ ]]; then
 
-      IOMUXGEN=`realpath ${BIN_DIR_PATH}/python/pp3_eos_s3_iomux_config.py`
+      IOMUXGEN=`realpath ${SHARE_DIR_PATH}/scripts/pp3_eos_s3_iomux_config.py`
 
       IOMUX_JLINK="${PROJECT%.*}_iomux.jlink"
       IOMUX_OPENOCD="${PROJECT%.*}_iomux.openocd"

f4pga/wrappers/sh/quicklogic/generate_libfile.f4pga.sh

@@ -34,7 +34,7 @@ fi
 ARCH_DIR="$F4PGA_SHARE_DIR"/arch/${DEVICE_1}_${DEVICE_1}
 PINMAP_XML=${ARCH_DIR}/${PINMAPXML}
 
-`which python3` "$F4PGA_BIN_DIR"/python/create_lib.py \
+`which python3` "$F4PGA_SHARE_DIR"/scripts/create_lib.py \
   -n ${DEV}_0P72_SSM40 \
   -m fpga_top \
   -c $PART \

f4pga/wrappers/sh/quicklogic/ql.f4pga.sh

@@ -361,7 +361,7 @@ else
   PCF_MAKE="\${current_dir}/${BUILDDIR}/${TOP}_dummy.pcf"
 fi
 
-PROCESS_SDC=$(realpath "$F4PGA_BIN_DIR"/python/process_sdc_constraints.py)
+PROCESS_SDC=$(realpath "$F4PGA_SHARE_DIR"/scripts/process_sdc_constraints.py)
 if ! [ -z "$SDC" ]; then
   if ! [ -f "$SOURCE"/$SDC ];then
     echo "The sdc file: $SDC is missing at: $SOURCE"

f4pga/wrappers/sh/quicklogic/repack.f4pga.sh

@@ -30,9 +30,9 @@ DESIGN=${EBLIF/.eblif/}
 [ ! -z "${JSON}" ] && JSON_ARGS="--json-constraints ${JSON}" || JSON_ARGS=
 [ ! -z "${PCF_PATH}" ] && PCF_ARGS="--pcf-constraints ${PCF_PATH}" || PCF_ARGS=
 
-export PYTHONPATH=$F4PGA_BIN_DIR/python:$PYTHONPATH
+export PYTHONPATH=$F4PGA_SHARE_DIR/scripts:$PYTHONPATH
 
-`which python3` "$F4PGA_BIN_DIR"/python/repacker/repack.py \
+`which python3` "$F4PGA_SHARE_DIR"/scripts/repacker/repack.py \
   --vpr-arch ${ARCH_DEF} \
   --repacking-rules ${ARCH_DIR}/${DEVICE_1}.repacking_rules.json \
   $JSON_ARGS \

f4pga/wrappers/sh/quicklogic/synth.f4pga.sh

@@ -20,8 +20,8 @@ set -e
 
 export SHARE_DIR_PATH=${SHARE_DIR_PATH:="$F4PGA_SHARE_DIR"}
 VPRPATH=${VPRPATH:="$F4PGA_BIN_DIR"}
-SPLIT_INOUTS=`realpath ${VPRPATH}/python/split_inouts.py`
-CONVERT_OPTS=`realpath ${VPRPATH}/python/convert_compile_opts.py`
+SPLIT_INOUTS=`realpath ${SHARE_DIR_PATH}/scripts/split_inouts.py`
+CONVERT_OPTS=`realpath ${SHARE_DIR_PATH}/scripts/convert_compile_opts.py`
 
 print_usage () {
     echo "Usage: symbiflow_synth  -v|--verilog <Verilog file list>"