f4pga/wrappers/sh: cleanup
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
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@ -464,7 +464,6 @@
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"$F4PGA_INSTALL_DIR": "${shareDir}/../../../../",
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"$FPGA_FAM": "eos-s3",
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"$PATH": "${shareDir}/../../../conda/envs/eos-s3/bin/:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin",
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"$SHARE_DIR_PATH": "${shareDir}",
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"$BIN_DIR_PATH": "${binDir}"
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}
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}
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@ -70,7 +70,7 @@ def p_vpr_common_cmds(log_suffix = None):
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return f"""
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set -e
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source {ROOT / SH_SUBDIR}/vpr_common.f4pga.sh
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parse_args {' '.join(sys_argv[1:])}
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parse_args {' '.join([f"'{arg}'" for arg in sys_argv[1:]])}
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""" + (f"""
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export OUT_NOISY_WARNINGS=noisy_warnings-${{DEVICE}}_{log_suffix}.log
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""" if log_suffix is not None else '')
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@ -112,6 +112,8 @@ def p_vpr_run():
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raise(Exception('[F4PGA] vpr run: envvar PLACE_DELAY cannot be unset/empty!'))
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sdc = f4pga_environ.get('SDC')
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if sdc == '':
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sdc = None
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check_call(
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[
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@ -18,8 +18,6 @@
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set -e
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SHARE_DIR_PATH=${SHARE_DIR_PATH:-"$F4PGA_SHARE_DIR"}
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source $(dirname "$0")/vpr_common.f4pga.sh
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VERSION="v2.0.1"
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@ -196,10 +194,8 @@ if [[ $1 == "-compile" || $1 == "-post_verilog" ]]; then
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fi
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fi
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if [ ! -z "$SOURCE" ]; then
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if [ ! -d $SOURCE/$BUILDDIR ]; then
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if [ ! -z "$SOURCE" ] && [ ! -d $SOURCE/$BUILDDIR ]; then
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mkdir -p $SOURCE/$BUILDDIR
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fi
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fi
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if [ ! -z "$OUT" ]; then
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@ -302,7 +298,7 @@ else
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PCF_MAKE="\${current_dir}/${BUILDDIR}/${TOP}_dummy.pcf"
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fi
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PROCESS_SDC=$(realpath "$F4PGA_SHARE_DIR"/scripts/process_sdc_constraints.py)
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PROCESS_SDC="$F4PGA_SHARE_DIR"/scripts/process_sdc_constraints.py
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if ! [ -z "$SDC" ]; then
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if ! [ -f "$SOURCE"/$SDC ];then
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echo "The sdc file: $SDC is missing at: $SOURCE"
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@ -18,9 +18,8 @@
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set -e
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export SHARE_DIR_PATH=${SHARE_DIR_PATH:-"$F4PGA_SHARE_DIR"}
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SPLIT_INOUTS=`realpath ${SHARE_DIR_PATH}/scripts/split_inouts.py`
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CONVERT_OPTS=`realpath ${SHARE_DIR_PATH}/scripts/convert_compile_opts.py`
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SPLIT_INOUTS="${F4PGA_SHARE_DIR}"/scripts/split_inouts.py
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CONVERT_OPTS="${F4PGA_SHARE_DIR}"/scripts/convert_compile_opts.py
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print_usage () {
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echo "Usage: symbiflow_synth -v|--verilog <Verilog file list>"
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@ -122,10 +121,10 @@ fi
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PINMAPCSV="pinmap_${PART}.csv"
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export TECHMAP_PATH="${SHARE_DIR_PATH}/techmaps/${FAMILY}"
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export TECHMAP_PATH="${F4PGA_SHARE_DIR}/techmaps/${FAMILY}"
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SYNTH_TCL_PATH="${SHARE_DIR_PATH}/scripts/${FAMILY}/synth.tcl"
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CONV_TCL_PATH="${SHARE_DIR_PATH}/scripts/${FAMILY}/conv.tcl"
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SYNTH_TCL_PATH="${F4PGA_SHARE_DIR}/scripts/${FAMILY}/synth.tcl"
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CONV_TCL_PATH="${F4PGA_SHARE_DIR}/scripts/${FAMILY}/conv.tcl"
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export USE_ROI="FALSE"
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export OUT_JSON=$TOP.json
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@ -134,7 +133,7 @@ export OUT_SYNTH_V=${TOP}_synth.v
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export OUT_EBLIF=${TOP}.eblif
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export OUT_FASM_EXTRA=${TOP}_fasm_extra.fasm
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export PYTHON3=$(which python3)
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export UTILS_PATH=${SHARE_DIR_PATH}/scripts
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export UTILS_PATH="${F4PGA_SHARE_DIR}"/scripts
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if [ -s $PCF ]; then
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export PCF_FILE=$PCF
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@ -142,7 +141,7 @@ else
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export PCF_FILE=""
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fi
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DEVICE_PATH="${SHARE_DIR_PATH}/arch/${DEVICE}_${DEVICE}"
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DEVICE_PATH="${F4PGA_SHARE_DIR}/arch/${DEVICE}_${DEVICE}"
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export PINMAP_FILE=${DEVICE_PATH}/${PINMAPCSV}
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if [ -d "${DEVICE_PATH}/cells" ]; then
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export DEVICE_CELLS_SIM=`find ${DEVICE_PATH}/cells -name "*_sim.v"`
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@ -151,7 +150,7 @@ else
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# pp3 family has different directory naming scheme
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# the are named as ${DEVICE}_${PACKAGE}
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# ${PACKAGE} is not known because it is not passed down in add_binary_toolchain_test
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DEVICE_PATH=$(find $(realpath ${SHARE_DIR_PATH}/arch/) -type d -name "${DEVICE}*")
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DEVICE_PATH=$(find "${F4PGA_SHARE_DIR}"/arch/ -type d -name "${DEVICE}*")
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export PINMAP_FILE=${DEVICE_PATH}/${PINMAPCSV}
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if [ -d "${DEVICE_PATH}/cells" ]; then
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export DEVICE_CELLS_SIM=`find ${DEVICE_PATH}/cells -name "*_sim.v"`
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@ -16,8 +16,6 @@
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#
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# SPDX-License-Identifier: Apache-2.0
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SHARE_DIR_PATH=${SHARE_DIR_PATH:-"$F4PGA_SHARE_DIR"}
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if [ -z $VPR_OPTIONS ]; then
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echo "Using default VPR options."
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VPR_OPTIONS="
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@ -118,7 +116,7 @@ function parse_args {
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fi
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DEVICE_ARCH="${DEVICE_1}_${DEVICE_2}"
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export ARCH_DIR=`realpath ${SHARE_DIR_PATH}/arch/${DEVICE_ARCH}`
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export ARCH_DIR="${F4PGA_SHARE_DIR}/arch/${DEVICE_ARCH}"
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export ARCH_DEF="${ARCH_DIR}/arch_${DEVICE_ARCH}".xml
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ARCH_RR_PREFIX="${ARCH_DIR}/rr_graph_${DEVICE_ARCH}"
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# qlf* devices use different naming scheme than pp3* ones.
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@ -18,10 +18,9 @@
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set -e
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export SHARE_DIR_PATH="$F4PGA_SHARE_DIR"
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export TECHMAP_PATH=${SHARE_DIR_PATH}/techmaps/xc7_vpr/techmap
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export TECHMAP_PATH="${F4PGA_SHARE_DIR}"/techmaps/xc7_vpr/techmap
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export UTILS_PATH=${SHARE_DIR_PATH}/scripts
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export UTILS_PATH="${F4PGA_SHARE_DIR}"/scripts
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SYNTH_TCL_PATH=${UTILS_PATH}/xc7/synth.tcl
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VERILOG_FILES=()
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@ -16,9 +16,7 @@
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#
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# SPDX-License-Identifier: Apache-2.0
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SHARE_DIR_PATH=${SHARE_DIR_PATH:-"$F4PGA_SHARE_DIR"}
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if [ -z $VPR_OPTIONS ]; then
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if [ -z "$VPR_OPTIONS" ]; then
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echo "Using default VPR options."
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VPR_OPTIONS="
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--max_router_iterations 500
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@ -76,13 +74,13 @@ function parse_args {
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esac
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done
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if [ -z $DEVICE ] && [ -n $PART ]; then
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if [ -z "$DEVICE" ] && [ -n "$PART" ]; then
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# Try to find device name. Accept only when exactly one is found
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PART_DIRS=(${SHARE_DIR_PATH}/arch/*/${PART})
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PART_DIRS=(${F4PGA_SHARE_DIR}/arch/*/${PART})
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if [ ${#PART_DIRS[@]} -eq 1 ]; then DEVICE=$(basename $(dirname "${PART_DIRS[0]}")); fi
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fi
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if [ -z $DEVICE ]; then echo "Please provide device name"; exit 1; fi
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if [ -z $EBLIF ]; then echo "Please provide blif file name"; exit 1; fi
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if [ -z "$DEVICE" ]; then echo "Please provide device name"; exit 1; fi
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if [ -z "$EBLIF" ]; then echo "Please provide blif file name"; exit 1; fi
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export DEVICE="$DEVICE"
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export EBLIF="$EBLIF"
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@ -91,7 +89,7 @@ function parse_args {
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export SDC="$SDC"
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export VPR_OPTIONS="$VPR_OPTIONS $ADDITIONAL_VPR_OPTIONS"
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export ARCH_DIR=`realpath ${SHARE_DIR_PATH}/arch/$DEVICE`
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export ARCH_DIR="${F4PGA_SHARE_DIR}/arch/$DEVICE"
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export ARCH_DEF="${ARCH_DIR}"/arch.timing.xml
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ARCH_RR_PREFIX="${ARCH_DIR}/rr_graph_${DEVICE}"
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export RR_GRAPH="${ARCH_RR_PREFIX}".rr_graph.real.bin
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