f4pga/wrappers/sh: cleanup

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral 2022-08-11 06:03:21 +02:00
parent 6dc738fd3d
commit 453fffea4e
7 changed files with 23 additions and 32 deletions

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@ -464,7 +464,6 @@
"$F4PGA_INSTALL_DIR": "${shareDir}/../../../../",
"$FPGA_FAM": "eos-s3",
"$PATH": "${shareDir}/../../../conda/envs/eos-s3/bin/:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin",
"$SHARE_DIR_PATH": "${shareDir}",
"$BIN_DIR_PATH": "${binDir}"
}
}

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@ -70,7 +70,7 @@ def p_vpr_common_cmds(log_suffix = None):
return f"""
set -e
source {ROOT / SH_SUBDIR}/vpr_common.f4pga.sh
parse_args {' '.join(sys_argv[1:])}
parse_args {' '.join([f"'{arg}'" for arg in sys_argv[1:]])}
""" + (f"""
export OUT_NOISY_WARNINGS=noisy_warnings-${{DEVICE}}_{log_suffix}.log
""" if log_suffix is not None else '')
@ -112,6 +112,8 @@ def p_vpr_run():
raise(Exception('[F4PGA] vpr run: envvar PLACE_DELAY cannot be unset/empty!'))
sdc = f4pga_environ.get('SDC')
if sdc == '':
sdc = None
check_call(
[

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@ -18,8 +18,6 @@
set -e
SHARE_DIR_PATH=${SHARE_DIR_PATH:-"$F4PGA_SHARE_DIR"}
source $(dirname "$0")/vpr_common.f4pga.sh
VERSION="v2.0.1"
@ -196,10 +194,8 @@ if [[ $1 == "-compile" || $1 == "-post_verilog" ]]; then
fi
fi
if [ ! -z "$SOURCE" ]; then
if [ ! -d $SOURCE/$BUILDDIR ]; then
if [ ! -z "$SOURCE" ] && [ ! -d $SOURCE/$BUILDDIR ]; then
mkdir -p $SOURCE/$BUILDDIR
fi
fi
if [ ! -z "$OUT" ]; then
@ -302,7 +298,7 @@ else
PCF_MAKE="\${current_dir}/${BUILDDIR}/${TOP}_dummy.pcf"
fi
PROCESS_SDC=$(realpath "$F4PGA_SHARE_DIR"/scripts/process_sdc_constraints.py)
PROCESS_SDC="$F4PGA_SHARE_DIR"/scripts/process_sdc_constraints.py
if ! [ -z "$SDC" ]; then
if ! [ -f "$SOURCE"/$SDC ];then
echo "The sdc file: $SDC is missing at: $SOURCE"

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@ -18,9 +18,8 @@
set -e
export SHARE_DIR_PATH=${SHARE_DIR_PATH:-"$F4PGA_SHARE_DIR"}
SPLIT_INOUTS=`realpath ${SHARE_DIR_PATH}/scripts/split_inouts.py`
CONVERT_OPTS=`realpath ${SHARE_DIR_PATH}/scripts/convert_compile_opts.py`
SPLIT_INOUTS="${F4PGA_SHARE_DIR}"/scripts/split_inouts.py
CONVERT_OPTS="${F4PGA_SHARE_DIR}"/scripts/convert_compile_opts.py
print_usage () {
echo "Usage: symbiflow_synth -v|--verilog <Verilog file list>"
@ -122,10 +121,10 @@ fi
PINMAPCSV="pinmap_${PART}.csv"
export TECHMAP_PATH="${SHARE_DIR_PATH}/techmaps/${FAMILY}"
export TECHMAP_PATH="${F4PGA_SHARE_DIR}/techmaps/${FAMILY}"
SYNTH_TCL_PATH="${SHARE_DIR_PATH}/scripts/${FAMILY}/synth.tcl"
CONV_TCL_PATH="${SHARE_DIR_PATH}/scripts/${FAMILY}/conv.tcl"
SYNTH_TCL_PATH="${F4PGA_SHARE_DIR}/scripts/${FAMILY}/synth.tcl"
CONV_TCL_PATH="${F4PGA_SHARE_DIR}/scripts/${FAMILY}/conv.tcl"
export USE_ROI="FALSE"
export OUT_JSON=$TOP.json
@ -134,7 +133,7 @@ export OUT_SYNTH_V=${TOP}_synth.v
export OUT_EBLIF=${TOP}.eblif
export OUT_FASM_EXTRA=${TOP}_fasm_extra.fasm
export PYTHON3=$(which python3)
export UTILS_PATH=${SHARE_DIR_PATH}/scripts
export UTILS_PATH="${F4PGA_SHARE_DIR}"/scripts
if [ -s $PCF ]; then
export PCF_FILE=$PCF
@ -142,7 +141,7 @@ else
export PCF_FILE=""
fi
DEVICE_PATH="${SHARE_DIR_PATH}/arch/${DEVICE}_${DEVICE}"
DEVICE_PATH="${F4PGA_SHARE_DIR}/arch/${DEVICE}_${DEVICE}"
export PINMAP_FILE=${DEVICE_PATH}/${PINMAPCSV}
if [ -d "${DEVICE_PATH}/cells" ]; then
export DEVICE_CELLS_SIM=`find ${DEVICE_PATH}/cells -name "*_sim.v"`
@ -151,7 +150,7 @@ else
# pp3 family has different directory naming scheme
# the are named as ${DEVICE}_${PACKAGE}
# ${PACKAGE} is not known because it is not passed down in add_binary_toolchain_test
DEVICE_PATH=$(find $(realpath ${SHARE_DIR_PATH}/arch/) -type d -name "${DEVICE}*")
DEVICE_PATH=$(find "${F4PGA_SHARE_DIR}"/arch/ -type d -name "${DEVICE}*")
export PINMAP_FILE=${DEVICE_PATH}/${PINMAPCSV}
if [ -d "${DEVICE_PATH}/cells" ]; then
export DEVICE_CELLS_SIM=`find ${DEVICE_PATH}/cells -name "*_sim.v"`

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@ -16,8 +16,6 @@
#
# SPDX-License-Identifier: Apache-2.0
SHARE_DIR_PATH=${SHARE_DIR_PATH:-"$F4PGA_SHARE_DIR"}
if [ -z $VPR_OPTIONS ]; then
echo "Using default VPR options."
VPR_OPTIONS="
@ -118,7 +116,7 @@ function parse_args {
fi
DEVICE_ARCH="${DEVICE_1}_${DEVICE_2}"
export ARCH_DIR=`realpath ${SHARE_DIR_PATH}/arch/${DEVICE_ARCH}`
export ARCH_DIR="${F4PGA_SHARE_DIR}/arch/${DEVICE_ARCH}"
export ARCH_DEF="${ARCH_DIR}/arch_${DEVICE_ARCH}".xml
ARCH_RR_PREFIX="${ARCH_DIR}/rr_graph_${DEVICE_ARCH}"
# qlf* devices use different naming scheme than pp3* ones.

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@ -18,10 +18,9 @@
set -e
export SHARE_DIR_PATH="$F4PGA_SHARE_DIR"
export TECHMAP_PATH=${SHARE_DIR_PATH}/techmaps/xc7_vpr/techmap
export TECHMAP_PATH="${F4PGA_SHARE_DIR}"/techmaps/xc7_vpr/techmap
export UTILS_PATH=${SHARE_DIR_PATH}/scripts
export UTILS_PATH="${F4PGA_SHARE_DIR}"/scripts
SYNTH_TCL_PATH=${UTILS_PATH}/xc7/synth.tcl
VERILOG_FILES=()

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@ -16,9 +16,7 @@
#
# SPDX-License-Identifier: Apache-2.0
SHARE_DIR_PATH=${SHARE_DIR_PATH:-"$F4PGA_SHARE_DIR"}
if [ -z $VPR_OPTIONS ]; then
if [ -z "$VPR_OPTIONS" ]; then
echo "Using default VPR options."
VPR_OPTIONS="
--max_router_iterations 500
@ -76,13 +74,13 @@ function parse_args {
esac
done
if [ -z $DEVICE ] && [ -n $PART ]; then
if [ -z "$DEVICE" ] && [ -n "$PART" ]; then
# Try to find device name. Accept only when exactly one is found
PART_DIRS=(${SHARE_DIR_PATH}/arch/*/${PART})
PART_DIRS=(${F4PGA_SHARE_DIR}/arch/*/${PART})
if [ ${#PART_DIRS[@]} -eq 1 ]; then DEVICE=$(basename $(dirname "${PART_DIRS[0]}")); fi
fi
if [ -z $DEVICE ]; then echo "Please provide device name"; exit 1; fi
if [ -z $EBLIF ]; then echo "Please provide blif file name"; exit 1; fi
if [ -z "$DEVICE" ]; then echo "Please provide device name"; exit 1; fi
if [ -z "$EBLIF" ]; then echo "Please provide blif file name"; exit 1; fi
export DEVICE="$DEVICE"
export EBLIF="$EBLIF"
@ -91,7 +89,7 @@ function parse_args {
export SDC="$SDC"
export VPR_OPTIONS="$VPR_OPTIONS $ADDITIONAL_VPR_OPTIONS"
export ARCH_DIR=`realpath ${SHARE_DIR_PATH}/arch/$DEVICE`
export ARCH_DIR="${F4PGA_SHARE_DIR}/arch/$DEVICE"
export ARCH_DEF="${ARCH_DIR}"/arch.timing.xml
ARCH_RR_PREFIX="${ARCH_DIR}/rr_graph_${DEVICE}"
export RR_GRAPH="${ARCH_RR_PREFIX}".rr_graph.real.bin