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Simplify synth module, always user read_verilog 

Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
This commit is contained in:
Krzysztof Boronski 2022-09-06 19:26:37 +02:00 committed by Unai Martinez-Corral
parent 9e327656a1
commit 5350ec87f7
1 changed files with 5 additions and 11 deletions
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12
f4pga/flows/common_modules/synth.py
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@ -53,16 +53,10 @@ class SynthModule(Module):
def execute(self, ctx: ModuleContext):
yield f"Synthesizing sources{f': {ctx.takes.sources}...' if get_verbosity_level() >= 2 else f'...'}"
tcl = f"tcl {str(get_tcl_wrapper_path())}"
verilog_files = []
# Use append read_verilog commands to the scripts for more sophisticated
# input if arguments are specified. Omit direct input throught `yosys` command.
if ctx.values.read_verilog_args:
args_str = " ".join(ctx.values.read_verilog_args)
tcl = f'tcl {str(get_tcl_wrapper_path("synth"))}'
args_str = " ".join(ctx.values.read_verilog_args) if ctx.values.read_verilog_args is not None else ""
for vfile in ctx.takes.sources:
tcl = f"read_verilog {args_str} {vfile}; {tcl}"
else:
verilog_files = ctx.takes.sources
# Set up environment for TCL weirdness
env = environ.copy()
@ -80,7 +74,7 @@ class SynthModule(Module):
# Execute YOSYS command
common_sub(
*(["yosys", "-p", tcl] + (["-l", ctx.outputs.synth_log] if ctx.outputs.synth_log else []) + verilog_files),
*(["yosys", "-p", tcl] + (["-l", ctx.outputs.synth_log] if ctx.outputs.synth_log else [])),
env=env,
)