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f4pga/common_modules/place: use pathlib instead of os and shutil 

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral 2022-08-15 07:23:19 +02:00
parent 52c44000cf
commit 5d919e9dc6
1 changed files with 4 additions and 7 deletions
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11
f4pga/common_modules/place.py
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@ -18,8 +18,6 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
from pathlib import Path from pathlib import Path
import os
from shutil import move as sh_mv
from re import match as re_match from re import match as re_match
from f4pga.common import vpr_specific_values, vpr as common_vpr, VprArgs, save_vpr_log from f4pga.common import vpr_specific_values, vpr as common_vpr, VprArgs, save_vpr_log
@ -50,10 +48,10 @@ class PlaceModule(Module):
def execute(self, ctx: ModuleContext): def execute(self, ctx: ModuleContext):
place_constraints, dummy = place_constraints_file(ctx) place_constraints, dummy = place_constraints_file(ctx)
place_constraints = os.path.realpath(place_constraints) place_constraints = Path(place_constraints).resolve()
if dummy: if dummy:
with open(place_constraints, 'wb') as f: with place_constraints.open('wb') as wfptr:
f.write(b'') wfptr.write(b'')
build_dir = Path(ctx.takes.eblif).parent build_dir = Path(ctx.takes.eblif).parent
@ -78,8 +76,7 @@ class PlaceModule(Module):
# modules may produce some temporary files with names that differ from # modules may produce some temporary files with names that differ from
# the ones in flow configuration. # the ones in flow configuration.
if ctx.is_output_explicit('place'): if ctx.is_output_explicit('place'):
output_file = default_output_name(place_constraints) Path(default_output_name(str(place_constraints))).rename(ctx.outputs.place)
sh_mv(output_file, ctx.outputs.place)
yield 'Saving log...' yield 'Saving log...'
save_vpr_log('place.log', build_dir=str(build_dir)) save_vpr_log('place.log', build_dir=str(build_dir))