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Add ice40 flow and yosys synthesis script
Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
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f4pga
51
f4pga/aux/tool_data/yosys/scripts/vendor/lattice/ice40/synth.tcl
vendored
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51
f4pga/aux/tool_data/yosys/scripts/vendor/lattice/ice40/synth.tcl
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@ -0,0 +1,51 @@
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# Copyright (C) 2022 F4PGA Authors
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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yosys -import
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plugin -i fasm
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# Import the commands from the plugins to the tcl interpreter
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yosys -import
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f4pga value top
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f4pga value part_name
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f4pga value yosys_plugins?
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f4pga take sources
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f4pga take build_dir
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f4pga produce json ${f4pga_build_dir}/${f4pga_top}.json -meta "Yosys JSON netlist"
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f4pga produce synth_v ${f4pga_build_dir}/${f4pga_top}_premap.v -meta "Pre-technology mapped structural verilog"
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if { [contains $f4pga_yosys_plugins uhdm] } {
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foreach {sysverilog_source} $f4pga_sources {
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read_verilog_with_uhdm $surelog_cmd $sysverilog_source
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}
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} else {
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foreach {verilog_source} $f4pga_sources {
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read_verilog $verilog_source
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}
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}
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synth_ice40 -nocarry
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opt_expr -undriven
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opt_clean
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attrmap -remove hdlname
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setundef -zero -params
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write_json $f4pga_json
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write_verilog $f4pga_synth_v
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@ -180,6 +180,41 @@ xc7a200t:
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vpr_options: *xc7-vpr_options
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ice40:
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values:
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nextpnr_options:
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hx1k: true
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stages:
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mk_build_dir:
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module: 'common:mkdirs'
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params:
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build_dir: build/${device}
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synth:
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module: 'common:yosys'
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params:
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tcl_script: "${auxDir}/tool_data/yosys/scripts/vendor/lattice/ice40/synth.tcl"
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pnr:
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module: 'ice40:nextpnr'
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values:
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placer: heap
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router: router1
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bitstream:
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module: 'common:generic_script_wrapper'
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params:
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stage_name: bitstream
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script: icepack
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outputs:
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bitstream:
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mode: file
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file: "${:ice_asm[noext]}.bit"
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target: "${:ice_asm[noext]}.bit"
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inputs:
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"#1": "${:ice_asm}"
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"#2": "${:ice_asm[noext]}.bit"
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ql-eos-s3:
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values:
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