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Add information about inverter logic in techmaps 

Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
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Robert Winkler 2020-09-28 11:14:08 +02:00
parent 2db5d5beb6
commit 747740a6b1
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source/toolchain-desc/yosys.rst
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@ -360,6 +360,15 @@ the ``BUFGCTRL_VPR``:
endmodule
.. note::
All SymbiFlow techmaps for Xilinx 7-Series devices use special inverter
logic that converts constant 0 signals at the BEL to constant-1 signals
at the site. This behavior is desired since VCC is the default signal in
7-Series and US/US+ devices. The presented solution matches the conventions
used by the vendor tools and gives the opportunity to validate generated
bitstreams with fasm2bels and Vivado.
Yosys provides special techmapping naming conventions for wires,
parameters, and modules. The special names that start with ``_TECHMAP_``
can be used to force certain behavior during the techmapping process.