f4pga/module_runner: import importlib.util explicitly

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral 2022-03-01 22:52:01 +01:00
parent 3ab6f2b10d
commit 898eab8232
1 changed files with 7 additions and 6 deletions

View File

@ -2,6 +2,7 @@
from contextlib import contextmanager
import importlib
import importlib.util
import os
from sf_module import Module, ModuleContext, get_mod_metadata
from sf_common import ResolutionEnv, deep, sfprint
@ -36,7 +37,7 @@ def get_module(path: str):
cached = preloaded_modules.get(path)
if cached:
return cached.ModuleClass
mod = import_module_from_path(path)
preloaded_modules[path] = mod
@ -53,7 +54,7 @@ class ModRunCtx:
self.share = share
self.bin = bin
self.config = config
def make_r_env(self):
return ResolutionEnv(self.config['values'])
@ -66,7 +67,7 @@ class ModuleFailException(Exception):
self.module = module
self.mode = mode
self.e = e
def __str__(self) -> str:
return f'ModuleFailException:\n Module `{self.module}` failed ' \
f'MODE: \'{self.mode}\'\n\nException `{type(self.e)}`: {self.e}'
@ -81,11 +82,11 @@ def module_io(module: Module):
def module_map(module: Module, ctx: ModRunCtx):
try:
mod_ctx = ModuleContext(module, ctx.config, ctx.make_r_env(), ctx.share,
mod_ctx = ModuleContext(module, ctx.config, ctx.make_r_env(), ctx.share,
ctx.bin)
except Exception as e:
raise ModuleFailException(module.name, 'map', e)
return _realpath_deep(vars(mod_ctx.outputs))
def module_exec(module: Module, ctx: ModRunCtx):
@ -94,7 +95,7 @@ def module_exec(module: Module, ctx: ModRunCtx):
ctx.bin)
except Exception as e:
raise ModuleFailException(module.name, 'exec', e)
sfprint(1, 'Executing module '
f'`{Style.BRIGHT + module.name + Style.RESET_ALL}`:')
current_phase = 1