use intersphinx instead of adding submodules

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>

.gitmodules

@@ -1,20 +1,3 @@
-[submodule "source/prjtrellis"]
-	path = source/prjtrellis
-	url = https://github.com/SymbiFlow/prjtrellis
-        branch = master
-[submodule "source/symbiflow-arch-defs"]
-	path = source/symbiflow-arch-defs
-	url = https://github.com/SymbiFlow/symbiflow-arch-defs
-        branch = master
-[submodule "source/prjxray"]
-	path = source/prjxray
-	url = https://github.com/SymbiFlow/prjxray
-[submodule "source/fasm"]
-	path = source/fasm
-	url = https://github.com/SymbiFlow/fasm
-[submodule "source/vtr-verilog-to-routing"]
-	path = source/vtr-verilog-to-routing
-	url = https://github.com/SymbiFlow/vtr-verilog-to-routing
 [submodule "third_party/make-env"]
 	path = third_party/make-env
 	url = https://github.com/SymbiFlow/make-env/

source/conf.py

@@ -26,6 +26,7 @@ sys.path.append(os.path.abspath('./vtr-verilog-to-routing/doc/_exts'))
 # Add any Sphinx extension module names here, as strings. They can be extensions
 # coming with Sphinx (named 'sphinx.ext.*') or your custom ones.
 extensions = [
+    'sphinx.ext.intersphinx',
     'sphinx.ext.todo',
     'sphinx.ext.autodoc',
     'sphinx.ext.imgmath',  # breathe
@@ -350,3 +351,14 @@ def prjxray_fuzzers_and_minitests_links():
     subprocess.call(cmd, shell=True)
 
 prjxray_fuzzers_and_minitests_links()
+
+# -- Sphinx.Ext.InterSphinx --------------------------------------------------------------------------------------------
+
+intersphinx_mapping = {
+    "python": ("https://docs.python.org/3/", None),
+    "arch-defs": ("https://symbiflow.readthedocs.io/projects/arch-defs/en/latest/", None),
+    "fasm": ("https://fasm.readthedocs.io/en/latest/", None),
+    "prjtrellis": ("https://prjtrellis.readthedocs.io/en/latest/", None),
+    "prjxray": ("https://symbiflow.readthedocs.io/projects/prjxray/en/latest/", None),
+    "vtr": ("https://docs.verilogtorouting.org/en/latest/", None),
+}

source/fasm

@@ -1 +0,0 @@
-Subproject commit 6308864592c6aacd5b87de5486b498a6ddde72b1

source/index.rst

@@ -6,8 +6,8 @@ SymbiFlow documentation
    :maxdepth: 3
 
    introduction
-   toolchain-desc
-   symbiflow-arch-defs/docs/source/index
-   prjxray/docs/index
-   prjtrellis/docs/index
-   fasm/docs/specification
+   toolchain-desc/index
+   Architecture Definitions ➚ <https://symbiflow.readthedocs.io/projects/arch-defs/en/latest/>
+   Project X-Ray ➚ <https://symbiflow.readthedocs.io/projects/prjxray/en/latest/>
+   Project Trellis ➚ <https://prjtrellis.readthedocs.io/en/latest/>
+   FPGPA Assembly (FASM) ➚ <https://fasm.readthedocs.io/en/latest/>

source/introduction.rst

@@ -37,16 +37,16 @@ project for several activities, the central of which pertains to the
 creation of so-called FPGA "architecture definitions",
 i.e. documentation of how specific FPGAs work internally.
 More information can be found in the :doc:`Symbiflow Architecture Definitions
-<../symbiflow-arch-defs/docs/source/index>` project.
+<arch-defs:index>` project.
 
 Those definitions and serve as input to backend tools like
 `nextpnr <https://github.com/YosysHQ/nextpnr>`_ and
 `Verilog to Routing <https://verilogtorouting.org/>`_, and frontend tools
 like `Yosys <http://www.clifford.at/yosys/>`_. They are created within separate
 collaborating projects targeting different FPGAs - :doc:`Project X-Ray
-<../prjxray/docs/index>` for Xilinx 7-Series, `Project IceStorm
+<prjxray:index>` for Xilinx 7-Series, `Project IceStorm
 <http://www.clifford.at/icestorm/>`_ for Lattice iCE40 and :doc:`Project Trellis
-<../prjtrellis/docs/index>` for Lattice ECP5 FPGAs.
+<prjtrellis:index>` for Lattice ECP5 FPGAs.
 
 .. figure:: images/parts.svg
 

source/prjtrellis

@@ -1 +0,0 @@
-Subproject commit 9b3db7ba9a02e7d2f49c52ce062d5b22e320004c

source/prjxray

@@ -1 +0,0 @@
-Subproject commit f7f06896ad26bb7c94680dc323d4b871eded1f4e

source/symbiflow-arch-defs

@@ -1 +0,0 @@
-Subproject commit b483f25497c4ea8e23916fa6788b85f6f7ea6981

source/toolchain-desc/index.rst

@@ -7,7 +7,7 @@ as well as the basic concepts of the FPGA design flow.
 .. toctree::
    :maxdepth: 3
 
-   symbiflow-arch-defs/docs/source/getting-started
-   toolchain-desc/design-flow
-   toolchain-desc/yosys
-   vtr-verilog-to-routing/doc/src/vpr/index
+   Getting started ➚ <https://symbiflow.readthedocs.io/projects/arch-defs/en/latest/getting-started.html>
+   design-flow
+   yosys
+   VPR ➚ <https://docs.verilogtorouting.org/en/latest/vpr/>

source/vtr-verilog-to-routing

@@ -1 +0,0 @@
-Subproject commit d58f993d07fe752dbe254132e739ce2d62abc9e5