use intersphinx instead of adding submodules

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral 2022-02-10 01:45:12 +01:00
parent 6881ed1cf8
commit a0a406e301
10 changed files with 24 additions and 34 deletions

17
.gitmodules vendored
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@ -1,20 +1,3 @@
[submodule "source/prjtrellis"]
path = source/prjtrellis
url = https://github.com/SymbiFlow/prjtrellis
branch = master
[submodule "source/symbiflow-arch-defs"]
path = source/symbiflow-arch-defs
url = https://github.com/SymbiFlow/symbiflow-arch-defs
branch = master
[submodule "source/prjxray"]
path = source/prjxray
url = https://github.com/SymbiFlow/prjxray
[submodule "source/fasm"]
path = source/fasm
url = https://github.com/SymbiFlow/fasm
[submodule "source/vtr-verilog-to-routing"]
path = source/vtr-verilog-to-routing
url = https://github.com/SymbiFlow/vtr-verilog-to-routing
[submodule "third_party/make-env"] [submodule "third_party/make-env"]
path = third_party/make-env path = third_party/make-env
url = https://github.com/SymbiFlow/make-env/ url = https://github.com/SymbiFlow/make-env/

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@ -26,6 +26,7 @@ sys.path.append(os.path.abspath('./vtr-verilog-to-routing/doc/_exts'))
# Add any Sphinx extension module names here, as strings. They can be extensions # Add any Sphinx extension module names here, as strings. They can be extensions
# coming with Sphinx (named 'sphinx.ext.*') or your custom ones. # coming with Sphinx (named 'sphinx.ext.*') or your custom ones.
extensions = [ extensions = [
'sphinx.ext.intersphinx',
'sphinx.ext.todo', 'sphinx.ext.todo',
'sphinx.ext.autodoc', 'sphinx.ext.autodoc',
'sphinx.ext.imgmath', # breathe 'sphinx.ext.imgmath', # breathe
@ -350,3 +351,14 @@ def prjxray_fuzzers_and_minitests_links():
subprocess.call(cmd, shell=True) subprocess.call(cmd, shell=True)
prjxray_fuzzers_and_minitests_links() prjxray_fuzzers_and_minitests_links()
# -- Sphinx.Ext.InterSphinx --------------------------------------------------------------------------------------------
intersphinx_mapping = {
"python": ("https://docs.python.org/3/", None),
"arch-defs": ("https://symbiflow.readthedocs.io/projects/arch-defs/en/latest/", None),
"fasm": ("https://fasm.readthedocs.io/en/latest/", None),
"prjtrellis": ("https://prjtrellis.readthedocs.io/en/latest/", None),
"prjxray": ("https://symbiflow.readthedocs.io/projects/prjxray/en/latest/", None),
"vtr": ("https://docs.verilogtorouting.org/en/latest/", None),
}

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Subproject commit 6308864592c6aacd5b87de5486b498a6ddde72b1

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@ -6,8 +6,8 @@ SymbiFlow documentation
:maxdepth: 3 :maxdepth: 3
introduction introduction
toolchain-desc toolchain-desc/index
symbiflow-arch-defs/docs/source/index Architecture Definitions ➚ <https://symbiflow.readthedocs.io/projects/arch-defs/en/latest/>
prjxray/docs/index Project X-Ray ➚ <https://symbiflow.readthedocs.io/projects/prjxray/en/latest/>
prjtrellis/docs/index Project Trellis ➚ <https://prjtrellis.readthedocs.io/en/latest/>
fasm/docs/specification FPGPA Assembly (FASM) ➚ <https://fasm.readthedocs.io/en/latest/>

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@ -37,16 +37,16 @@ project for several activities, the central of which pertains to the
creation of so-called FPGA "architecture definitions", creation of so-called FPGA "architecture definitions",
i.e. documentation of how specific FPGAs work internally. i.e. documentation of how specific FPGAs work internally.
More information can be found in the :doc:`Symbiflow Architecture Definitions More information can be found in the :doc:`Symbiflow Architecture Definitions
<../symbiflow-arch-defs/docs/source/index>` project. <arch-defs:index>` project.
Those definitions and serve as input to backend tools like Those definitions and serve as input to backend tools like
`nextpnr <https://github.com/YosysHQ/nextpnr>`_ and `nextpnr <https://github.com/YosysHQ/nextpnr>`_ and
`Verilog to Routing <https://verilogtorouting.org/>`_, and frontend tools `Verilog to Routing <https://verilogtorouting.org/>`_, and frontend tools
like `Yosys <http://www.clifford.at/yosys/>`_. They are created within separate like `Yosys <http://www.clifford.at/yosys/>`_. They are created within separate
collaborating projects targeting different FPGAs - :doc:`Project X-Ray collaborating projects targeting different FPGAs - :doc:`Project X-Ray
<../prjxray/docs/index>` for Xilinx 7-Series, `Project IceStorm <prjxray:index>` for Xilinx 7-Series, `Project IceStorm
<http://www.clifford.at/icestorm/>`_ for Lattice iCE40 and :doc:`Project Trellis <http://www.clifford.at/icestorm/>`_ for Lattice iCE40 and :doc:`Project Trellis
<../prjtrellis/docs/index>` for Lattice ECP5 FPGAs. <prjtrellis:index>` for Lattice ECP5 FPGAs.
.. figure:: images/parts.svg .. figure:: images/parts.svg

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@ -7,7 +7,7 @@ as well as the basic concepts of the FPGA design flow.
.. toctree:: .. toctree::
:maxdepth: 3 :maxdepth: 3
symbiflow-arch-defs/docs/source/getting-started Getting started ➚ <https://symbiflow.readthedocs.io/projects/arch-defs/en/latest/getting-started.html>
toolchain-desc/design-flow design-flow
toolchain-desc/yosys yosys
vtr-verilog-to-routing/doc/src/vpr/index VPR ➚ <https://docs.verilogtorouting.org/en/latest/vpr/>

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