Merge pull request #546 from antmicro/umarcor/docs/https

docs: s/http:/https:/

LICENSE

@@ -1,7 +1,7 @@
 
                                  Apache License
                            Version 2.0, January 2004
-                        http://www.apache.org/licenses/
+                        https://www.apache.org/licenses/
 
    TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
 
@@ -193,7 +193,7 @@
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at
 
-       http://www.apache.org/licenses/LICENSE-2.0
+       https://www.apache.org/licenses/LICENSE-2.0
 
    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,

docs/flows/f4pga.rst

@@ -134,7 +134,7 @@ Technology mapping in F4PGA toolchain
 
 .. _Xilinx 7 Series FPGAs Clocking Resources User Guide: https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf#page=38
 .. _VTR FPGA Architecture Description: https://docs.verilogtorouting.org/en/latest/arch/
-.. _techmap section in the Yosys Manual: http://yosyshq.net/yosys/files/yosys_manual.pdf#page=153
+.. _techmap section in the Yosys Manual: https://yosyshq.net/yosys/files/yosys_manual.pdf#page=153
 
 It is important to understand the connection between the synthesis and
 implementation tools used in the F4PGA toolchain. As mentioned before,
@@ -190,7 +190,7 @@ Below you can see the pb_type XML for ``BUFGCTRL_VPR`` primitive:
 .. code-block:: xml
 
    <!-- Model of BUFG group in BUFG_CLK_TOP/BOT -->
-   <pb_type name="BLK-TL-BUFGCTRL" xmlns:xi="http://www.w3.org/2001/XInclude">
+   <pb_type name="BLK-TL-BUFGCTRL" xmlns:xi="https://www.w3.org/2001/XInclude">
      <output name="O" num_pins="1"/>
      <input name="CE0" num_pins="1"/>
      <input name="CE1" num_pins="1"/>
@@ -406,7 +406,7 @@ More information
 
 Additional information about Yosys can be found on the `Yosys Project Website
 <https://yosyshq.net/yosys/>`_ , or in `Yosys Manual
-<http://yosyshq.net/yosys/files/yosys_manual.pdf>`_. You can also compile
+<https://yosyshq.net/yosys/files/yosys_manual.pdf>`_. You can also compile
 one of the tests described in Getting Started section and watch the log file
 to understand which operations are performed by Yosys.
 

docs/how.rst

@@ -33,7 +33,7 @@ Thus, F4PGA serves as an umbrella project for several activities.
 The central resources are the so-called FPGA "architecture definitions" (i.e. documentation of how specific FPGAs work
 internally) and the "interchange schema" (for logical and physical netlists).
 Those definitions serve as input to frontend and backend tools, such as
-`Yosys ➚ <http://yosyshq.net/yosys/>`__,
+`Yosys ➚ <https://yosyshq.net/yosys/>`__,
 :gh:`nextpnr ➚ <YosysHQ/nextpnr>` and `Verilog to Routing ➚ <https://verilogtorouting.org/>`_.
 They are created within separate collaborating projects targeting different FPGAs:
 
@@ -55,7 +55,7 @@ To prepare a working bitstream for a particular FPGA chip, the toolchain goes th
     This stage is typically pre-built and installed as assets.
     However, developers contributing to the bitstream documentation might build it.
 
-* Then, logic synthesis is carried out in the `Yosys ➚ <http://yosyshq.net/yosys/>`__ framework, which expresses the
+* Then, logic synthesis is carried out in the `Yosys ➚ <https://yosyshq.net/yosys/>`__ framework, which expresses the
   user-provided hardware description by means of the block and connection types available in the chosen chip.
 
 * The next step is implementation.

docs/refs.bib

@@ -102,7 +102,7 @@
   author = {Stallman, Richard and {contributors}},
   year = {1987},
   title = {{GCC, the GNU Compiler Collection}},
-  url = {http://gcc.gnu.org/},
+  url = {https://gcc.gnu.org/},
   month = {May},
 }
 

docs/requirements.txt

@@ -1,5 +1,5 @@
 sphinx>=4.5.0
 sphinxcontrib-bibtex
-http://github.com/SymbiFlow/sphinx_symbiflow_theme/archive/chips.zip#sphinx-symbiflow-theme
-http://github.com/SymbiFlow/sphinx-verilog-domain/archive/master.zip#sphinx-verilog-domain
+https://github.com/SymbiFlow/sphinx_symbiflow_theme/archive/chips.zip#sphinx-symbiflow-theme
+https://github.com/SymbiFlow/sphinx-verilog-domain/archive/master.zip#sphinx-verilog-domain
 tabulate

docs/status.rst

@@ -5,7 +5,7 @@ Supported Architectures
 * `Xilinx 7-Series <https://www.xilinx.com/video/fpga/7-series-fpga-overview.html>`__:
   the most popular Xilinx FPGA family.
 
-* `Lattice ice40 <http://www.latticesemi.com/iCE40>`__:
+* `Lattice ice40 <https://www.latticesemi.com/iCE40>`__:
   world's smallest FPGAs for mobile devices.
 
 * `Lattice ecp5 <https://www.latticesemi.com/Products/FPGAandCPLD/ECP5>`__: