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f4pga
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modules: synth: use pathlib 

Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
This commit is contained in:
Pawel Czarnecki 2022-07-11 09:27:27 +02:00 committed by Unai Martinez-Corral
parent e4f0639f8d
commit ab4b7a6c61
1 changed files with 7 additions and 6 deletions
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13
f4pga/common_modules/synth.py
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@ -18,6 +18,7 @@
# SPDX-License-Identifier: Apache-2.0
import os
from pathlib import Path
from f4pga.common import *
from f4pga.module import Module, ModuleContext
@ -99,20 +100,20 @@ class SynthModule(Module):
def execute(self, ctx: ModuleContext):
tcl_env = yosys_setup_tcl_env(ctx.values.yosys_tcl_env) \
if ctx.values.yosys_tcl_env else {}
split_inouts = os.path.join(tcl_env["UTILS_PATH"], 'split_inouts.py')
synth_tcl = os.path.join(ctx.values.tcl_scripts, 'synth.tcl')
conv_tcl = os.path.join(ctx.values.tcl_scripts, 'conv.tcl')
split_inouts = Path(tcl_env["UTILS_PATH"]) / 'split_inouts.py'
synth_tcl = Path(ctx.values.tcl_scripts) / 'synth.tcl'
conv_tcl = Path(ctx.values.tcl_scripts) / 'conv.tcl'
if get_verbosity_level() >= 2:
yield f'Synthesizing sources: {ctx.takes.sources}...'
else:
yield f'Synthesizing sources...'
yosys_synth(synth_tcl, tcl_env, ctx.takes.sources,
yosys_synth(str(synth_tcl), tcl_env, ctx.takes.sources,
ctx.values.read_verilog_args, ctx.outputs.synth_log)
yield f'Splitting in/outs...'
sub('python3', split_inouts, '-i', ctx.outputs.json, '-o',
sub('python3', str(split_inouts), '-i', ctx.outputs.json, '-o',
ctx.outputs.synth_json)
if not os.path.isfile(ctx.produces.fasm_extra):
@ -120,7 +121,7 @@ class SynthModule(Module):
f.write('')
yield f'Converting...'
yosys_conv(conv_tcl, tcl_env, ctx.outputs.synth_json)
yosys_conv(str(conv_tcl), tcl_env, ctx.outputs.synth_json)
def __init__(self, params):
self.name = 'synthesize'