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f4pga/wrappers/sh/quicklogic: cleanup and adjust 

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral 2022-03-20 02:28:33 +01:00
parent 6dbdcee076
commit ac82b068e1
11 changed files with 352 additions and 418 deletions
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15
f4pga/wrappers/sh/quicklogic/analysis.f4pga.sh
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@ -1,23 +1,22 @@
#!/bin/bash
#!/usr/bin/env bash
set -e
MYPATH=`realpath $0`
MYPATH=`dirname ${MYPATH}`
if [ -z $VPRPATH ]; then
export VPRPATH=$(f4pga-env bin)
export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH}
fi
source ${MYPATH}/env
source ${VPRPATH}/vpr_common
parse_args $@
FIXUP_POST_SYNTHESIS=`realpath ${MYPATH}/python/vpr_fixup_post_synth.py`
export OUT_NOISY_WARNINGS=noisy_warnings-${DEVICE}_analysis.log
run_vpr --analysis --gen_post_synthesis_netlist on --verify_file_digests off
mv vpr_stdout.log analysis.log
python3 ${FIXUP_POST_SYNTHESIS} \
python3 $(f4pga-env bin)/python/vpr_fixup_post_synth.py \
--vlog-in ${TOP}_post_synthesis.v \
--vlog-out ${TOP}_post_synthesis.v \
--sdf-in ${TOP}_post_synthesis.sdf \

37
f4pga/wrappers/sh/quicklogic/generate_bitstream.f4pga.sh
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@ -1,8 +1,6 @@
#!/bin/bash
set -e
#!/usr/bin/env bash
MYPATH=`realpath $0`
MYPATH=`dirname ${MYPATH}`
set -e
OPTS=d:f:r:b:
LONGOPTS=device:,fasm:,format:,bit:
@ -17,25 +15,11 @@ BIT_FORMAT="4byte"
while true; do
case "$1" in
-d|--device)
DEVICE=$2
shift 2
;;
-f|--fasm)
FASM=$2
shift 2
;;
-r|--format)
BIT_FORMAT=$2
shift 2
;;
-b|--bit)
BIT=$2
shift 2
;;
--)
break
;;
-d|--device) DEVICE=$2; shift 2;;
-f|--fasm) FASM=$2; shift 2;;
-r|--format) BIT_FORMAT=$2; shift 2;;
-b|--bit) BIT=$2; shift 2;;
--) break;;
esac
done
@ -54,9 +38,6 @@ if [ -z $BIT ]; then
exit 1
fi
QLF_FASM=`which qlf_fasm`
DB_ROOT=`realpath ${MYPATH}/../share/symbiflow/fasm_database/${DEVICE}`
${QLF_FASM} --db-root ${DB_ROOT} --format ${BIT_FORMAT} --assemble $FASM $BIT
DB_ROOT=$(f4pga-env share)/fasm_database/${DEVICE}
`which qlf_fasm` --db-root ${DB_ROOT} --format ${BIT_FORMAT} --assemble $FASM $BIT

20
f4pga/wrappers/sh/quicklogic/generate_constraints.f4pga.sh
View File

@ -1,8 +1,6 @@
#!/bin/bash
set -e
#!/usr/bin/env bash
MYPATH=`realpath $0`
MYPATH=`dirname ${MYPATH}`
set -e
PCF=$1
EBLIF=$2
@ -22,9 +20,17 @@ else
DEVICE_1=${DEVICE}
fi
PINMAP_XML=`realpath ${MYPATH}/../share/symbiflow/arch/${DEVICE_1}_${DEVICE_1}/${PINMAPXML}`
IOGEN=`realpath ${MYPATH}/python/create_ioplace.py`
SHARE_DIR_PATH=${SHARE_DIR_PATH:=$(f4pga-env share)}
PINMAP_XML=`realpath ${SHARE_DIR_PATH}/arch/${DEVICE_1}_${DEVICE_1}/${PINMAPXML}`
PROJECT=$(basename -- "$EBLIF")
IOPLACE_FILE="${PROJECT%.*}_io.place"
python3 ${IOGEN} --pcf $PCF --blif $EBLIF --pinmap_xml $PINMAP_XML --csv_file $PART --net $NET > ${IOPLACE_FILE}
python3 $(realpath $(f4pga-env bin)/python/create_ioplace.py) \
--pcf $PCF \
--blif $EBLIF \
--pinmap_xml $PINMAP_XML \
--csv_file $PART \
--net $NET \
> ${IOPLACE_FILE}

20
f4pga/wrappers/sh/quicklogic/generate_libfile.f4pga.sh
View File

@ -1,8 +1,6 @@
#!/bin/bash
set -e
#!/usr/bin/env bash
MYPATH=`realpath $0`
MYPATH=`dirname ${MYPATH}`
set -e
PART=$1
DEVICE=$2
@ -17,9 +15,13 @@ else
DEVICE_1=${DEVICE}
fi
ARCH_DIR=`realpath ${MYPATH}/../share/symbiflow/arch/${DEVICE_1}_${DEVICE_1}`
PINMAP_XML=`realpath ${ARCH_DIR}/${PINMAPXML}`
INTF_XML=`realpath ${ARCH_DIR}/lib/${INTERFACEXML}`
CREATE_LIB=`realpath ${MYPATH}/python/create_lib.py`
ARCH_DIR=$(f4pga-env share)/arch/${DEVICE_1}_${DEVICE_1}
PINMAP_XML=${ARCH_DIR}/${PINMAPXML}
python3 ${CREATE_LIB} -n ${DEV}_0P72_SSM40 -m fpga_top -c $PART -x $INTF_XML -l ${DEV}_0P72_SSM40.lib -t ${ARCH_DIR}/lib
python3 $(f4pga-env bin)/python/create_lib.py \
-n ${DEV}_0P72_SSM40 \
-m fpga_top \
-c $PART \
-x ${ARCH_DIR}/lib/${INTERFACEXML} \
-l ${DEV}_0P72_SSM40.lib \
-t ${ARCH_DIR}/lib

11
f4pga/wrappers/sh/quicklogic/pack.f4pga.sh
View File

@ -1,12 +1,13 @@
#!/bin/bash
#!/usr/bin/env bash
set -e
MYPATH=`realpath $0`
MYPATH=`dirname ${MYPATH}`
if [ -z $VPRPATH ]; then
export VPRPATH=$(f4pga-env bin)
export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH}
fi
source ${MYPATH}/env
source ${VPRPATH}/vpr_common
parse_args $@
export OUT_NOISY_WARNINGS=noisy_warnings-${DEVICE}_pack.log

32
f4pga/wrappers/sh/quicklogic/place.f4pga.sh
View File

@ -1,12 +1,13 @@
#!/bin/bash
#!/usr/bin/env bash
set -e
MYPATH=`realpath $0`
MYPATH=`dirname ${MYPATH}`
source ${MYPATH}/env
source ${MYPATH}/vpr_common
if [ -z $VPRPATH ]; then
export VPRPATH=$(f4pga-env bin)
export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH}
fi
source ${VPRPATH}/vpr_common
parse_args $@
if [ -z $PCF ]; then
@ -21,28 +22,21 @@ fi
OUT_NOISY_WARNINGS=noisy_warnings-${DEVICE}_place.log
PROJECT=$(basename -- "$EBLIF")
# Generate IO constraints
if [ -s $PCF ]; then
echo "Generating constraints ..."
symbiflow_generate_constraints $PCF $EBLIF $NET $PART $DEVICE $ARCH_DEF $CORNER
IOPLACE_FILE="${PROJECT%.*}_io.place"
PLACE_FILE="${PROJECT%.*}_constraints.place"
if [ -s $PCF ]; then
# Generate IO constraints
echo "Generating constraints ..."
symbiflow_generate_constraints $PCF $EBLIF $NET $PART $DEVICE $ARCH_DEF $CORNER
if [ -f ${PLACE_FILE} ]; then
VPR_PLACE_FILE=${PLACE_FILE}
else
VPR_PLACE_FILE=${IOPLACE_FILE}
VPR_PLACE_FILE="${PROJECT%.*}_io.place"
fi
# Make a dummy empty constraint file
else
PLACE_FILE="${PROJECT%.*}_constraints.place"
# Make a dummy empty constraint file
touch ${PLACE_FILE}
VPR_PLACE_FILE=${PLACE_FILE}
fi
run_vpr --fix_clusters ${VPR_PLACE_FILE} --place

124
f4pga/wrappers/sh/quicklogic/ql.f4pga.sh
View File

@ -1,13 +1,11 @@
#!/bin/bash
#!/usr/bin/env bash
set -e
MYPATH=$(dirname "$(readlink -f "$BASH_SOURCE")")
BUILDDIR=build
source ${MYPATH}/env
source ${VPRPATH}/vpr_common
source $(f4pga-env bin)/vpr_common
VERSION="v2.0.1"
if [ ! -n $1 ]; then
@ -51,106 +49,74 @@ COMPILE_EXTRA_ARGS=()
OPT=""
for arg in $@; do
case $arg in
-src|--source)
OPT="src"
;;
-t|--top)
OPT="top"
;;
-v|--verilog)
OPT="vlog"
;;
-d|--device)
OPT="dev"
;;
-p|--pcf)
OPT="pcf"
;;
-P|--part)
OPT="part"
;;
-j|--json)
OPT="json"
;;
-s|--sdc)
OPT="sdc"
;;
-r|--route_type)
OPT="route"
;;
-pnr_corner)
OPT="pnr_corner"
;;
-analysis_corner)
OPT="analysis_corner"
;;
-dump)
OPT="dump"
;;
-synth|-compile)
OPT="synth"
;;
-y|+incdir+*|+libext+*|+define+*)
OPT="compile_xtra"
;;
-f)
OPT="options_file"
;;
-h|--help)
exit 0
;;
-src|--source) OPT="src" ;;
-t|--top) OPT="top" ;;
-v|--verilog) OPT="vlog" ;;
-d|--device) OPT="dev" ;;
-p|--pcf) OPT="pcf" ;;
-P|--part) OPT="part" ;;
-j|--json) OPT="json" ;;
-s|--sdc) OPT="sdc" ;;
-r|--route_type) OPT="route" ;;
-pnr_corner) OPT="pnr_corner" ;;
-analysis_corner) OPT="analysis_corner" ;;
-dump) OPT="dump" ;;
-synth|-compile) OPT="synth" ;;
-y|+incdir+*|+libext+*|+define+*) OPT="compile_xtra" ;;
-f) OPT="options_file" ;;
-h|--help) exit 0 ;;
*)
case $OPT in
"src")
src)
SOURCE=$arg
OPT=""
;;
"top")
top)
TOP=$arg
OPT=""
;;
"vlog")
vlog)
VERILOG_FILES+="$arg "
;;
"dev")
dev)
DEVICE=$arg
OPT=""
;;
"pcf")
pcf)
PCF=$arg
OPT=""
;;
"part")
part)
PART=$arg
OPT=""
;;
"json")
json)
JSON=$arg
OPT=""
;;
"sdc")
sdc)
SDC=$arg
OPT=""
;;
"route")
route)
ROUTE_FLAG0="$arg"
ROUTE_FLAG0="${ROUTE_FLAG0,,}"
OPT=""
;;
"pnr_corner")
pnr_corner)
PNR_CORNER=$arg
OPT=""
;;
"analysis_corner")
analysis_corner)
ANALYSIS_CORNER=$arg
OPT=""
;;
"dump")
dump)
OUT+="$arg "
;;
"compile_xtra")
compile_xtra)
;;
"options_file")
options_file)
COMPILE_EXTRA_ARGS+=("-f \"`realpath $arg`\" ")
;;
*)
@ -160,11 +126,9 @@ for arg in $@; do
esac
;;
esac
if [ "$OPT" == "compile_xtra" ]; then
COMPILE_EXTRA_ARGS+=($arg)
fi
done
case ${DEVICE} in
@ -182,7 +146,7 @@ case ${DEVICE} in
;;
esac
##### Check if the source directory exists #####
## Check if the source directory exists
if [[ $1 == "-h" || $1 == "--help" ]];then
exit 1
else
@ -207,8 +171,7 @@ fi
echo "$VERILOG_FILES" >${SOURCE}/v_list
fi
##### Validate the verlog source files #####
## Validate the verlog source files
if [ ${#VERILOG_FILES[@]} -eq 0 ]; then
if [[ $1 != "-h" || $1 != "--help" ]];then
echo "Please provide at least one Verilog file"
@ -276,8 +239,7 @@ if [ ! -z "$OUT" ];then
OUT_ARR=($OUT)
fi
for item in $VERILOG_FILES;
do
for item in $VERILOG_FILES; do
if ! [ -f $SOURCE/$item ]; then
echo "$item: verilog file does not exists at : $SOURCE"
exit 1
@ -315,7 +277,8 @@ export JSON=$JSON
export TOP_F=$TOP
export PINMAP_FILE=$PINMAPCSV
export MAX_CRITICALITY=$MAX_CRITICALITY
##### Create Makefile #####
## Create Makefile
if [[ $SOURCE =~ ^/ ]]; then
CURR_DIR="${SOURCE}"
@ -362,7 +325,7 @@ else
PCF_MAKE="\${current_dir}/build/${TOP}_dummy.pcf"
fi
PROCESS_SDC=`realpath ${MYPATH}/python/process_sdc_constraints.py`
PROCESS_SDC=$(realpath $(f4pga-env bin)/python/process_sdc_constraints.py)
if ! [ -z "$SDC" ]; then
if ! [ -f "$SOURCE"/$SDC ];then
echo "The sdc file: $SDC is missing at: $SOURCE"
@ -459,10 +422,10 @@ clean:\n\
rm -rf \${BUILDDIR}\n\
" >>$MAKE_FILE
#### Remove temporary files #####
## Remove temporary files
rm -f $SOURCE/f_list_temp $SOURCE/v_list_tmp $SOURCE/v_list
##### Make file Targets #####
## Make file Targets
if [ $1 == "-synth" ]; then
echo -e "Performing Synthesis "
cd $SOURCE;make -f Makefile.symbiflow ${BUILDDIR}/${TOP}.eblif || exit
@ -476,8 +439,3 @@ else
cd $SOURCE;make -f Makefile.symbiflow ${BUILDDIR}/${TOP}.${RUN_TILL} || exit
fi
fi
###############################################################################################

29
f4pga/wrappers/sh/quicklogic/repack.f4pga.sh
View File

@ -1,32 +1,23 @@
#!/bin/bash
#!/usr/bin/env bash
set -e
MYPATH=`realpath $0`
MYPATH=`dirname ${MYPATH}`
if [ -z $VPRPATH ]; then
export VPRPATH=$(f4pga-env bin)
export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH}
fi
source ${MYPATH}/env
source ${VPRPATH}/vpr_common
parse_args $@
REPACK=`realpath ${MYPATH}/python/repacker/repack.py`
DESIGN=${EBLIF/.eblif/}
RULES=${ARCH_DIR}/${DEVICE_1}.repacking_rules.json
JSON_ARGS=
if [ ! -z "${JSON}" ]; then
JSON_ARGS="--json-constraints ${JSON}"
fi
[ ! -z "${JSON}" ] && JSON_ARGS="--json-constraints ${JSON}" || JSON_ARGS=
[ ! -z "${PCF_PATH}" ] && PCF_ARGS="--pcf-constraints ${PCF_PATH}" || PCF_ARGS=
PCF_ARGS=
if [ ! -z "${PCF_PATH}" ]; then
PCF_ARGS="--pcf-constraints ${PCF_PATH}"
fi
python3 ${REPACK} \
python3 $(f4pga-env bin)/python/repacker/repack.py \
--vpr-arch ${ARCH_DEF} \
--repacking-rules ${RULES} \
--repacking-rules ${ARCH_DIR}/${DEVICE_1}.repacking_rules.json \
$JSON_ARGS \
$PCF_ARGS \
--eblif-in ${DESIGN}.eblif \

13
f4pga/wrappers/sh/quicklogic/route.f4pga.sh
View File

@ -1,15 +1,16 @@
#!/bin/bash
#!/usr/bin/env bash
set -e
MYPATH=`realpath $0`
MYPATH=`dirname ${MYPATH}`
if [ -z $VPRPATH ]; then
export VPRPATH=$(f4pga-env bin)
export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH}
fi
source ${MYPATH}/env
source ${VPRPATH}/vpr_common
parse_args $@
export OUR_NOISY_WARNINGS=noisy_warnings-${DEVICE}_pack.log
export OUT_NOISY_WARNINGS=noisy_warnings-${DEVICE}_pack.log
run_vpr --route

22
f4pga/wrappers/sh/quicklogic/synth.f4pga.sh
View File

@ -1,11 +1,11 @@
#!/bin/bash
#!/usr/bin/env bash
set -e
MYPATH=`realpath $0`
MYPATH=`dirname ${MYPATH}`
SPLIT_INOUTS=`realpath ${MYPATH}/python/split_inouts.py`
CONVERT_OPTS=`realpath ${MYPATH}/python/convert_compile_opts.py`
export SHARE_DIR_PATH=${SHARE_DIR_PATH:=$(f4pga-env share)}
VPRPATH=${VPRPATH:=$(f4pga-env bin)}
SPLIT_INOUTS=`realpath ${VPRPATH}/python/split_inouts.py`
CONVERT_OPTS=`realpath ${VPRPATH}/python/convert_compile_opts.py`
print_usage () {
echo "Usage: symbiflow_synth -v|--verilog <Verilog file list>"
@ -107,10 +107,10 @@ fi
PINMAPCSV="pinmap_${PART}.csv"
export TECHMAP_PATH=`realpath ${MYPATH}/../share/symbiflow/techmaps/${FAMILY}`
export TECHMAP_PATH="${SHARE_DIR_PATH}/techmaps/${FAMILY}"
SYNTH_TCL_PATH=`realpath ${MYPATH}/../share/symbiflow/scripts/${FAMILY}/synth.tcl`
CONV_TCL_PATH=`realpath ${MYPATH}/../share/symbiflow/scripts/${FAMILY}/conv.tcl`
SYNTH_TCL_PATH="${SHARE_DIR_PATH}/scripts/${FAMILY}/synth.tcl"
CONV_TCL_PATH="${SHARE_DIR_PATH}/scripts/${FAMILY}/conv.tcl"
export USE_ROI="FALSE"
export OUT_JSON=$TOP.json
@ -123,7 +123,7 @@ if [ -s $PCF ]; then
export PCF_FILE=$PCF
fi
DEVICE_PATH=`realpath ${MYPATH}/../share/symbiflow/arch/${DEVICE}_${DEVICE}`
DEVICE_PATH="${SHARE_DIR_PATH}/arch/${DEVICE}_${DEVICE}"
export PINMAP_FILE=${DEVICE_PATH}/${PINMAPCSV}
if [ -d "${DEVICE_PATH}/cells" ]; then
export DEVICE_CELLS_SIM=`find ${DEVICE_PATH}/cells -name "*_sim.v"`
@ -132,7 +132,7 @@ else
# pp3 family has different directory naming scheme
# the are named as ${DEVICE}_${PACKAGE}
# ${PACKAGE} is not known because it is not passed down in add_binary_toolchain_test
DEVICE_PATH=$(find $(realpath ${MYPATH}/../share/symbiflow/arch/) -type d -name "${DEVICE}*")
DEVICE_PATH=$(find $(realpath ${SHARE_DIR_PATH}/arch/) -type d -name "${DEVICE}*")
export PINMAP_FILE=${DEVICE_PATH}/${PINMAPCSV}
if [ -d "${DEVICE_PATH}/cells" ]; then
export DEVICE_CELLS_SIM=`find ${DEVICE_PATH}/cells -name "*_sim.v"`

13
f4pga/wrappers/sh/quicklogic/write_fasm.f4pga.sh
View File

@ -1,16 +1,17 @@
#!/bin/bash
#!/usr/bin/env bash
set -e
MYPATH=`realpath $0`
MYPATH=`dirname ${MYPATH}`
if [ -z $VPRPATH ]; then
export VPRPATH=$(f4pga-env bin)
export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH}
fi
source ${MYPATH}/env
source ${VPRPATH}/vpr_common
parse_args "$@"
TOP="${EBLIF%.*}"
FASM_EXTRA=${TOP}_fasm_extra.fasm
FASM_EXTRA="${TOP}_fasm_extra.fasm"
export OUT_NOISY_WARNINGS=noisy_warnings-${DEVICE}_fasm.log