f4pga/flows: mv synth yosys

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral 2022-09-22 19:40:38 +01:00
parent c406d26b3a
commit bacc41ddd2
2 changed files with 7 additions and 7 deletions

View File

@ -29,7 +29,7 @@ from f4pga.wrappers.tcl import get_script_path as get_tcl_wrapper_path
isLattice = FPGA_FAM == "ice40"
class SynthModule(Module):
class YosysModule(Module):
extra_products: "list[str]"
def map_io(self, ctx: ModuleContext):
@ -99,7 +99,7 @@ class SynthModule(Module):
wfptr.write("")
def __init__(self, params):
self.name = "synthesize"
self.name = "yosys"
self.no_of_phases = 3
self.pnrtool = "nextpnr" if isLattice else "vpr"
@ -147,4 +147,4 @@ class SynthModule(Module):
self.prod_meta.update(extra_meta)
ModuleClass = SynthModule
ModuleClass = YosysModule

View File

@ -59,7 +59,7 @@ xc7a50t: &xc7
params:
build_dir: 'build/${device}'
synth:
module: 'common:synth'
module: 'common:yosys'
params:
takes:
- xdc?
@ -193,7 +193,7 @@ ice40:
params:
build_dir: build/${device}
synth:
module: 'common:synth'
module: 'common:yosys'
params:
takes:
produces:
@ -261,7 +261,7 @@ ql-eos-s3:
params:
build_dir: 'build/${device}'
synth:
module: 'common:synth'
module: 'common:yosys'
params:
takes:
- pcf?
@ -650,7 +650,7 @@ ql-k4n8_fast: &ql-k4n8
params:
build_dir: 'build/${device}'
synth:
module: 'common:synth'
module: 'common:yosys'
params:
produces:
- synth_v