f4pga/flows: mv synth yosys
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
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@ -29,7 +29,7 @@ from f4pga.wrappers.tcl import get_script_path as get_tcl_wrapper_path
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isLattice = FPGA_FAM == "ice40"
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class SynthModule(Module):
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class YosysModule(Module):
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extra_products: "list[str]"
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def map_io(self, ctx: ModuleContext):
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@ -99,7 +99,7 @@ class SynthModule(Module):
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wfptr.write("")
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def __init__(self, params):
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self.name = "synthesize"
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self.name = "yosys"
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self.no_of_phases = 3
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self.pnrtool = "nextpnr" if isLattice else "vpr"
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@ -147,4 +147,4 @@ class SynthModule(Module):
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self.prod_meta.update(extra_meta)
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ModuleClass = SynthModule
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ModuleClass = YosysModule
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@ -59,7 +59,7 @@ xc7a50t: &xc7
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params:
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build_dir: 'build/${device}'
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synth:
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module: 'common:synth'
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module: 'common:yosys'
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params:
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takes:
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- xdc?
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@ -193,7 +193,7 @@ ice40:
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params:
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build_dir: build/${device}
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synth:
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module: 'common:synth'
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module: 'common:yosys'
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params:
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takes:
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produces:
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@ -261,7 +261,7 @@ ql-eos-s3:
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params:
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build_dir: 'build/${device}'
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synth:
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module: 'common:synth'
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module: 'common:yosys'
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params:
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takes:
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- pcf?
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@ -650,7 +650,7 @@ ql-k4n8_fast: &ql-k4n8
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params:
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build_dir: 'build/${device}'
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synth:
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module: 'common:synth'
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module: 'common:yosys'
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params:
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produces:
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- synth_v
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