mirror of
https://github.com/chipsalliance/f4pga.git
synced 2025-01-03 03:43:37 -05:00
f4pga/flows: cleanup (#644)
This commit is contained in:
parent
6cb486e096
commit
e1cd038f06
7 changed files with 61 additions and 72 deletions
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@ -24,13 +24,6 @@ from json import dump as json_dump, load as json_load, JSONDecodeError
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from f4pga.flows.common import sfprint
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def _get_hash(path: Path):
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if not path.is_dir():
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with path.open("rb") as rfptr:
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return zlib_adler32(rfptr.read())
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return 0 # Directories always get '0' hash.
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class F4Cache:
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"""
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`F4Cache` is used to track changes among dependencies and keep the status of the files on a persistent storage.
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@ -76,7 +69,13 @@ class F4Cache:
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def process_file(self, path: Path):
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"""Process file for tracking with f4cache."""
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hash = _get_hash(path)
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if path.is_dir():
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# Directories always get '0' hash.
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hash = 0
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else:
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with path.open("rb") as rfptr:
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hash = zlib_adler32(rfptr.read())
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self.current_hashes[path.as_posix()] = hash
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def update(self, path: Path, consumer: str):
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@ -31,7 +31,7 @@ def open_flow_cfg(path: str) -> dict:
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return json_load(rfptr)
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def _get_ovs_raw(dict_name: str, flow_cfg, part: "str | None", stage: "str | None"):
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def p_get_ovs_raw(dict_name: str, flow_cfg, part: "str | None", stage: "str | None"):
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vals = flow_cfg.get(dict_name)
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if vals is None:
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vals = {}
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@ -55,11 +55,6 @@ def verify_platform_name(platform: str, mypath: str):
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return False
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def _is_kword(w: str):
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kwords = {"dependencies", "values", "default_platform", "default_target"}
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return w in kwords
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class FlowDefinition:
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stages: "dict[str, Stage]" # stage name -> module path mapping
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r_env: ResolutionEnv
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@ -80,6 +75,9 @@ class FlowDefinition:
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return self.stages.keys()
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KWORDS = {"dependencies", "values", "default_platform", "default_target"}
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class ProjectFlowConfig:
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flow_cfg: dict
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path: str
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@ -90,7 +88,7 @@ class ProjectFlowConfig:
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def parts(self):
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for part in self.flow_cfg.keys():
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if not _is_kword(part):
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if part not in KWORDS:
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yield part
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def get_default_part(self) -> "str | None":
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@ -103,13 +101,13 @@ class ProjectFlowConfig:
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"""
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Get dependencies without value resolution applied.
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"""
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return _get_ovs_raw("dependencies", self.flow_cfg, part, None)
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return p_get_ovs_raw("dependencies", self.flow_cfg, part, None)
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def get_values_raw(self, part: "str | None" = None, stage: "str | None" = None):
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"""
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Get values without value resolution applied.
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"""
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return _get_ovs_raw("values", self.flow_cfg, part, stage)
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return p_get_ovs_raw("values", self.flow_cfg, part, stage)
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def get_stage_value_overrides(self, part: str, stage: str):
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stage_vals_ovds = {}
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@ -155,7 +153,7 @@ def override_prj_flow_cfg_by_cli(cfg: ProjectFlowConfig, cli_d: "dict[str, dict[
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p_dependencies.update(cli_p_dependencies)
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for stage_name, cli_stage_cfg in part_cfg.items():
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if _is_kword(stage_name):
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if stage_name in KWORDS:
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continue
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stage_cfg = part_cfg.get(stage_name)
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@ -23,18 +23,18 @@ from f4pga.flows.module import Module
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from f4pga.flows.common import decompose_depname
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def _get_if_qualifier(deplist: "list[str]", qualifier: str):
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def p_get_if_qualifier(deplist: "list[str]", qualifier: str):
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for dep_name in deplist:
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name, q = decompose_depname(dep_name)
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if q == qualifier:
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yield f"● {Style.BRIGHT}{name}{Style.RESET_ALL}"
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def _list_if_qualifier(deplist: "list[str]", qualifier: str, indent: int = 4):
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def p_list_if_qualifier(deplist: "list[str]", qualifier: str, indent: int = 4):
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indent_str = "".join([" " for _ in range(0, indent)])
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r = ""
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for line in _get_if_qualifier(deplist, qualifier):
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for line in p_get_if_qualifier(deplist, qualifier):
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r += indent_str + line + "\n"
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return r
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@ -44,18 +44,18 @@ def get_module_info(module: Module) -> str:
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r = ""
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r += f"Module `{Style.BRIGHT}{module.name}{Style.RESET_ALL}`:\n"
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r += "Inputs:\n Required:\n Dependencies\n"
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r += _list_if_qualifier(module.takes, "req", indent=6)
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r += p_list_if_qualifier(module.takes, "req", indent=6)
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r += " Values:\n"
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r += _list_if_qualifier(module.values, "req", indent=6)
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r += p_list_if_qualifier(module.values, "req", indent=6)
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r += " Optional:\n Dependencies:\n"
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r += _list_if_qualifier(module.takes, "maybe", indent=6)
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r += p_list_if_qualifier(module.takes, "maybe", indent=6)
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r += " Values:\n"
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r += _list_if_qualifier(module.values, "maybe", indent=6)
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r += p_list_if_qualifier(module.values, "maybe", indent=6)
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r += "Outputs:\n Guaranteed:\n"
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r += _list_if_qualifier(module.produces, "req", indent=4)
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r += p_list_if_qualifier(module.produces, "req", indent=4)
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r += " On-demand:\n"
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r += _list_if_qualifier(module.produces, "demand", indent=4)
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r += p_list_if_qualifier(module.produces, "demand", indent=4)
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r += " Not guaranteed:\n"
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r += _list_if_qualifier(module.produces, "maybe", indent=4)
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r += p_list_if_qualifier(module.produces, "maybe", indent=4)
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return r
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@ -23,19 +23,11 @@ from f4pga.flows.tools.vpr import vpr_specific_values, vpr, VprArgs
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from f4pga.flows.module import Module, ModuleContext
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def analysis_merged_post_implementation_file(ctx: ModuleContext):
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return str(Path(ctx.takes.eblif).with_suffix("")) + "_merged_post_implementation.v"
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def analysis_post_implementation_file(ctx: ModuleContext):
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return str(Path(ctx.takes.eblif).with_suffix("")) + "_post_synthesis.v"
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class analysisModule(Module):
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def map_io(self, ctx: ModuleContext):
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return {
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"merged_post_implementation_v": analysis_merged_post_implementation_file(ctx),
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"post_implementation_v": analysis_post_implementation_file(ctx),
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"merged_post_implementation_v": p_analysis_merged_post_implementation_file(ctx),
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"post_implementation_v": p_analysis_post_implementation_file(ctx),
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}
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def execute(self, ctx: ModuleContext):
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@ -59,10 +51,10 @@ class analysisModule(Module):
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)
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if ctx.is_output_explicit("merged_post_implementation_v"):
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Path(analysis_merged_post_implementation_file(ctx)).rename(ctx.outputs.merged_post_implementation_v)
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Path(p_analysis_merged_post_implementation_file(ctx)).rename(ctx.outputs.merged_post_implementation_v)
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if ctx.is_output_explicit("post_implementation_v"):
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Path(analysis_post_implementation_file(ctx)).rename(ctx.outputs.post_implementation_v)
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Path(p_analysis_post_implementation_file(ctx)).rename(ctx.outputs.post_implementation_v)
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yield "Saving log..."
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save_vpr_log("analysis.log", build_dir=build_dir)
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@ -76,3 +68,11 @@ class analysisModule(Module):
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ModuleClass = analysisModule
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def p_analysis_merged_post_implementation_file(ctx: ModuleContext):
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return str(Path(ctx.takes.eblif).with_suffix("")) + "_merged_post_implementation.v"
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def p_analysis_post_implementation_file(ctx: ModuleContext):
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return str(Path(ctx.takes.eblif).with_suffix("")) + "_post_synthesis.v"
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@ -48,7 +48,7 @@ from f4pga.flows.module import Module, ModuleContext
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from f4pga.flows.runner import get_module
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def _switch_keys(d: "dict[str, ]", renames: "dict[str, str]") -> "dict[str, ]":
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def p_switch_keys(d: "dict[str, ]", renames: "dict[str, str]") -> "dict[str, ]":
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newd = {}
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for k, v in d.items():
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r = renames.get(k)
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@ -59,7 +59,7 @@ def _switch_keys(d: "dict[str, ]", renames: "dict[str, str]") -> "dict[str, ]":
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return newd
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def _switchback_attrs(d: Namespace, renames: "dict[str, str]") -> SimpleNamespace:
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def p_switchback_attrs(d: Namespace, renames: "dict[str, str]") -> SimpleNamespace:
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newn = SimpleNamespace()
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for k, v in vars(d).items():
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setattr(newn, k, v)
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@ -71,7 +71,7 @@ def _switchback_attrs(d: Namespace, renames: "dict[str, str]") -> SimpleNamespac
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return newn
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def _switch_entries(l: "list[str]", renames: "dict[str, str]") -> "list[str]":
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def p_switch_entries(l: "list[str]", renames: "dict[str, str]") -> "list[str]":
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newl = []
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for e in l:
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r = renames.get(e)
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return newl
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def _or_empty_dict(d: "dict | None"):
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def p_or_empty_dict(d: "dict | None"):
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return d if d is not None else {}
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@ -95,16 +95,16 @@ class IORenameModule(Module):
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def map_io(self, ctx: ModuleContext):
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newctx = ctx.shallow_copy()
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newctx.takes = _switchback_attrs(ctx.takes, self.rename_takes)
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newctx.values = _switchback_attrs(ctx.values, self.rename_values)
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newctx.takes = p_switchback_attrs(ctx.takes, self.rename_takes)
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newctx.values = p_switchback_attrs(ctx.values, self.rename_values)
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r = self.module.map_io(newctx)
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return _switch_keys(r, self.rename_produces)
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return p_switch_keys(r, self.rename_produces)
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def execute(self, ctx: ModuleContext):
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newctx = ctx.shallow_copy()
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newctx.takes = _switchback_attrs(ctx.takes, self.rename_takes)
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newctx.values = _switchback_attrs(ctx.values, self.rename_values)
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newctx.outputs = _switchback_attrs(ctx.produces, self.rename_produces)
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newctx.takes = p_switchback_attrs(ctx.takes, self.rename_takes)
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newctx.values = p_switchback_attrs(ctx.values, self.rename_values)
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newctx.outputs = p_switchback_attrs(ctx.produces, self.rename_produces)
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print(newctx.takes)
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return self.module.execute(newctx)
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@ -113,18 +113,18 @@ class IORenameModule(Module):
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module_class = get_module(mod_path)
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module: Module = module_class(params.get("params"))
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self.rename_takes = _or_empty_dict(params.get("rename_takes"))
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self.rename_produces = _or_empty_dict(params.get("rename_produces"))
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self.rename_values = _or_empty_dict(params.get("rename_values"))
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self.rename_takes = p_or_empty_dict(params.get("rename_takes"))
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self.rename_produces = p_or_empty_dict(params.get("rename_produces"))
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self.rename_values = p_or_empty_dict(params.get("rename_values"))
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self.module = module
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self.name = f"{module.name}-io_renamed"
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self.no_of_phases = module.no_of_phases
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self.takes = _switch_entries(module.takes, self.rename_takes)
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self.produces = _switch_entries(module.produces, self.rename_produces)
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self.values = _switch_entries(module.values, self.rename_values)
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self.takes = p_switch_entries(module.takes, self.rename_takes)
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self.produces = p_switch_entries(module.produces, self.rename_produces)
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self.values = p_switch_entries(module.values, self.rename_values)
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if hasattr(module, "prod_meta"):
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self.prod_meta = _switch_keys(module.prod_meta, self.rename_produces)
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self.prod_meta = p_switch_keys(module.prod_meta, self.rename_produces)
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ModuleClass = IORenameModule
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@ -24,21 +24,13 @@ from f4pga.flows.tools.vpr import vpr_specific_values, vpr, VprArgs, save_vpr_lo
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from f4pga.flows.module import Module, ModuleContext
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def default_output_name(eblif):
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return str(Path(eblif).with_suffix(".place"))
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def place_constraints_file(ctx: ModuleContext):
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if ctx.takes.place_constraints:
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return ctx.takes.place_constraints, False
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if ctx.takes.io_place:
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return ctx.takes.io_place, False
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return str(Path(ctx.takes.eblif).with_suffix(".place"))
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def p_default_output_name(eblif):
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return Path(eblif).with_suffix(".place")
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class PlaceModule(Module):
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def map_io(self, ctx: ModuleContext):
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return {"place": default_output_name(ctx.takes.eblif)}
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return {"place": str(p_default_output_name(ctx.takes.eblif))}
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def execute(self, ctx: ModuleContext):
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build_dir = ctx.takes.build_dir
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# modules may produce some temporary files with names that differ from
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# the ones in flow configuration.
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if ctx.is_output_explicit("place"):
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Path(default_output_name(ctx.takes.eblif)).rename(ctx.outputs.place)
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p_default_output_name(ctx.takes.eblif).rename(ctx.outputs.place)
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yield "Saving log..."
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save_vpr_log("place.log", build_dir=build_dir)
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@ -23,13 +23,13 @@ from f4pga.flows.tools.vpr import vpr_specific_values, vpr, VprArgs, save_vpr_lo
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from f4pga.flows.module import Module, ModuleContext
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def route_place_file(ctx: ModuleContext):
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def p_route_place_file(ctx: ModuleContext):
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return Path(ctx.takes.eblif).with_suffix(".route")
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class RouteModule(Module):
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def map_io(self, ctx: ModuleContext):
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return {"route": str(route_place_file(ctx))}
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return {"route": str(p_route_place_file(ctx))}
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def execute(self, ctx: ModuleContext):
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build_dir = Path(ctx.takes.eblif).parent
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@ -52,7 +52,7 @@ class RouteModule(Module):
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)
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if ctx.is_output_explicit("route"):
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route_place_file(ctx).rename(ctx.outputs.route)
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p_route_place_file(ctx).rename(ctx.outputs.route)
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yield "Saving log..."
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save_vpr_log("route.log", build_dir=build_dir)
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