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modules: synth: use UTILS_PATH env var for split_inouts.py path 

Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
This commit is contained in:
Paweł Czarnecki 2022-06-14 16:55:39 +02:00 committed by Unai Martinez-Corral
parent 7b7fa8ae3c
commit e4f0639f8d
1 changed files with 3 additions and 4 deletions
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7
f4pga/common_modules/synth.py
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@ -97,12 +97,11 @@ class SynthModule(Module):
return mapping return mapping
def execute(self, ctx: ModuleContext): def execute(self, ctx: ModuleContext):
split_inouts = os.path.join(ctx.share, 'scripts/split_inouts.py')
synth_tcl = os.path.join(ctx.values.tcl_scripts, 'synth.tcl')
conv_tcl = os.path.join(ctx.values.tcl_scripts, 'conv.tcl')
tcl_env = yosys_setup_tcl_env(ctx.values.yosys_tcl_env) \ tcl_env = yosys_setup_tcl_env(ctx.values.yosys_tcl_env) \
if ctx.values.yosys_tcl_env else {} if ctx.values.yosys_tcl_env else {}
split_inouts = os.path.join(tcl_env["UTILS_PATH"], 'split_inouts.py')
synth_tcl = os.path.join(ctx.values.tcl_scripts, 'synth.tcl')
conv_tcl = os.path.join(ctx.values.tcl_scripts, 'conv.tcl')
if get_verbosity_level() >= 2: if get_verbosity_level() >= 2:
yield f'Synthesizing sources: {ctx.takes.sources}...' yield f'Synthesizing sources: {ctx.takes.sources}...'