docs: use extlinks

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>

docs/community.rst

@@ -31,9 +31,9 @@ Communication
 Souces
 ======
 
-* `github.com/chipsalliance <https://github.com/chipsalliance/?q=f4pga>`__
+* :gh:`github.com/chipsalliance <chipsalliance/?q=f4pga>`
 
-* `github.com/F4PGA <https://github.com/F4PGA>`__
+* :gh:`github.com/F4PGA <F4PGA>`
 
 .. _Contributing:
 

docs/getting-started.rst

@@ -17,4 +17,4 @@ your FPGA.
 
   * `Project Trellis ➚ <https://prjtrellis.readthedocs.io/en/latest/>`__
 
-  * `Project Icestorm ➚ <https://github.com/f4pga/icestorm>`__
+  * :gh:`Project Icestorm ➚ <f4pga/icestorm>`

docs/how.rst

@@ -33,14 +33,13 @@ Thus, F4PGA serves as an umbrella project for several activities, the central of
 so-called FPGA "architecture definitions", i.e. documentation of how specific FPGAs work internally.
 More information can be found in the :doc:`F4PGA Architecture Definitions <arch-defs:index>` project.
 
-Those definitions and serve as input to backend tools like
+Those definitions and serve as input to backend tools like :gh:`nextpnr <YosysHQ/nextpnr>` and `Verilog to Routing <https://verilogtorouting.org/>`_,
-`nextpnr <https://github.com/YosysHQ/nextpnr>`_ and
+and frontend tools like `Yosys <http://www.clifford.at/yosys/>`_.
-`Verilog to Routing <https://verilogtorouting.org/>`_, and frontend tools
+They are created within separate collaborating projects targeting different FPGAs:
-like `Yosys <http://www.clifford.at/yosys/>`_. They are created within separate
+
-collaborating projects targeting different FPGAs - :doc:`Project X-Ray
+* :doc:`Project X-Ray <prjxray:index>` for Xilinx 7-Series
-<prjxray:index>` for Xilinx 7-Series, `Project IceStorm
+* `Project IceStorm <http://www.clifford.at/icestorm/>` for Lattice iCE40
-<http://www.clifford.at/icestorm/>`_ for Lattice iCE40 and :doc:`Project Trellis
+* :doc:`Project Trellis <prjtrellis:index>` for Lattice ECP5 FPGAs
-<prjtrellis:index>` for Lattice ECP5 FPGAs.
 
 .. figure:: _static/images/parts.svg
 
@@ -50,7 +49,7 @@ To prepare a working bitstream for a particular FPGA chip, the toolchain goes th
 
 * First, a description of the FPGA chip is created with the information from the relevant bitstream documentation
   project.
-  This part is done within the `F4PGA Architecture Definitions <https://github.com/chipsalliance/f4pga-arch-defs>`__.
+  This part is done within the :gh:`F4PGA Architecture Definitions <chipsalliance/f4pga-arch-defs>`.
   The project prepares information about the timings and resources available in the chip needed at the implementation
   stage, as well as techmaps for the synthesis tools.
 
@@ -61,9 +60,8 @@ To prepare a working bitstream for a particular FPGA chip, the toolchain goes th
 * The next step is implementation.
   Placement and routing tools put individual blocks from the synthesis description in the specific chip locations and
   create paths between them.
-  To do that, F4PGA uses either `nextpnr <https://github.com/YosysHQ/nextpnr>`__ or `Verilog to Routing <https://github.com/verilog-to-routing/vtr-verilog-to-routing>`__.
+  To do that, F4PGA uses either :gh:`nextpnr <YosysHQ/nextpnr>` or `Verilog to Routing :gh:<verilog-to-routing/vtr-verilog-to-routing>`.
 
 * Finally, the design properties are translated into a set of features available in the given FPGA chip.
-  These features are saved in the `fasm format <https://github.com/chipsalliance/fasm>`__, which is developed as part of
+  These features are saved in the :gh:`fasm format <chipsalliance/fasm>`, which is developed as part of F4PGA.
-  F4PGA.
   The fasm file is then translated to bitstream using the information from the bitstream documentation projects.

docs/yosys.rst

@@ -57,15 +57,13 @@ An example configuration script can be found below:
     write_blif -attr -cname -param $::env(OUT_EBLIF)
     write_verilog $::env(OUT_SYNTH_V)
 
-It can be seen that this script performs a platform-specific process of
+It can be seen that this script performs a platform-specific process of synthesis, some optimization steps (``opt_``
-synthesis, some optimization steps (``opt_`` commands), and writes the final file in
+commands), and writes the final file in ``.eblif`` and Verilog formats.
-``.eblif`` and Verilog formats. Yosys synthesis configuration scripts are platform-specific
+Yosys synthesis configuration scripts are platform-specific and can by found in ``<platform-dir>/yosys/synth.tcl`` in
-and can by found in ``<platform-dir>/yosys/synth.tcl``
+the :gh:`F4PGA Architecture Definitions <SymbiFlow/f4pga-arch-defs>` repository.
-in the `F4PGA Architecture Definitions <https://github.com/SymbiFlow/f4pga-arch-defs>`_
-repository.
 
-To understand performed operations, view the log file. It is usually generated
+To understand performed operations, view the log file.
-in the project build directory. It should be named ``top.eblif.log``.
+It is usually generated in the project build directory. It should be named ``top.eblif.log``.
 
 Output analysis
 ---------------