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docs/f4pga: convert README.md to rst pages
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
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docs/f4pga/Contributing.rst
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docs/f4pga/Contributing.rst
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Contributing
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############
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We welcome contributions from all people as long as they don't include any discriminatory, hateful language, don't force
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users to use proprietary technologies and are related to the F4PGA project.
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We will prioritize contributions which serve to improve support for platforms that are officially supported by ``f4pga``.
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UX-related contributions are welcome as well.
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Reporting bugs
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==============
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If you find a bug and want other to take a look, please open an issue, attach a log and a minimal example for
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reproducing the bug.
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Use ``-vv`` (maximum verbosity level) option when running ``f4pga`` if possible.
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Please, remember to specify the version of architecture definitions you are using (this applies only to VPR-based flows).
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If you used a pre-built packages, please provide a hash that identifies the package and name of the platform in question
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(*XC7*/*EOS-S3*).
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The hash is the last alphanumeric component before the ``.tar.gz`` suffix of the archive with prebuilt packages.
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Use your local installation to look-up the hash.
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Links to packages in :ref:`examples:Getting` get automatically updated to point to the latest packages.
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If you built the architecture definitions yourself, please specify the hash of the commit you've used.
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If you don't specify the version of architecture definitions, we might be unable to reproduce the bug.
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@ -1,93 +0,0 @@
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# f4pga python package
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This is the current in-development FPGA-oriented build system that's provided with f4pga.
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This package aims to provide a unified front-end for executing _verilog-to-bitstream_ and
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other flows for various FPGA platforms. It's meant as a future replacement of
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`symbiflow_*` shell scripts.
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It contains _EDA_ tool wrappers that provide meta-data about the tools, utilities
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related to tracking files and inspection of data used within the flows, scripts used by
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tools within flows, a dependency resolution algorithm and flow templates for various devices.
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The basic usage requires creation of a `flow.json` file describing the FPGA-oriented project.
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You can take
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[one from the f4pga-examples repository](https://github.com/chipsalliance/f4pga-examples/blob/main/xc7/counter_test/flow.json)
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as a reference. Alternatively there's a way to configure a flow with command-line parameters only.
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Once you have your flow created, run
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```
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f4pga build -f flow.json
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```
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to build a default target.
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To learn more about the package and its usage, visit
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[related section in the docs](https://f4pga.readthedocs.io/en/latest/f4pga/index.html).
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--------------------------------------------------
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## Package capability status:
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* Architecture support:
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* Xilinx XC7 (**available** in main branch)
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* Synthesis tool: yosys
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* PnR tool: VPR
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* bitstream generation: yes (xcfasm)
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* used in f4pga-examples:
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[yes](https://github.com/chipsalliance/f4pga-examples/blob/main/xc7/counter_test/flow.json)
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* Quicklogic EOS-S3 (yosys+VPR flow) (**WIP**, see
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[#577](https://github.com/chipsalliance/f4pga/pull/577))
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* Synthesis tool: yosys
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* PnR tool: VPR
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* bitstream generation: yes (qlfasm)
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* analysis: ?
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* used in f4pga-examples: no
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* Lattice ICE40 (yosys+nextpnr flow) (**WIP**, see
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[#585](https://github.com/chipsalliance/f4pga/pull/585))
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* Synthesis tool: yosys
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* PnR tool: nextpnr
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* bitstream generation: yes (icepack)
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* used in f4pga-examples: no
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* Quicklogic k4n8 (Unverified, not officially supported. Might work after some tinkering.)
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* Synthesis tool: yosys
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* PnR tool: VPR
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* bitstream generation: yes (qlf_fasm)
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* used in f4pga-examples: no
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* Incremental builds support
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* Support for multiple configurations for a single project
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* Can be used as a python interface to _F4PGA_, however there's no official _API_ at the moment.
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## Contributing
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We welcome contributions from all people as long as they don't include any discriminatory, hateful
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language, don't force users to use proprietary technologies and are related to the F4PGA project.
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We will prioritize contributions which serve to improve support for platforms that are
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officially supported by _f4pga_. UX-related contributions are welcome as well.
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## Reporting bugs
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If you find a bug and want other to take a look, please open an issue, attach a log and a minimal
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example for reproducing the bug. Use `-vv` (maximum verbosity level) option when running `f4pga`
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if possible.
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Please, remember to specify the version of architecture definitions you are using (this applies only to VPR-based flows).
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If you used a pre-built packages, please provide a hash that identifies the package and name
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of the platform in question (_XC7_/_EOS-S3_).
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The hash is the last alphanumeric component before the `.tar.gz` suffix of the archive with
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prebuilt packages. Use your local installation to look-up the hash. Links to packages in
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[the documention](https://f4pga-examples.readthedocs.io/en/latest/getting.html) get automatically
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updated to point to the latest packages.
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If you built the architecture definitions yourself, please specify the hash of the commit you've
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used.
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If you don't specify the version of architecture definitions, we might be unable to reproduce the
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bug.
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## Licensing
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f4pga is a Free Open-Source Software licensed under Apache 2.0 license.
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52
docs/f4pga/Status.rst
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52
docs/f4pga/Status.rst
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Package capability status
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#########################
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* Architecture support:
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* Xilinx XC7 (**available** in main branch)
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* Synthesis tool: yosys
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* PnR tool: VPR
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* bitstream generation: yes (xcfasm)
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* used in f4pga-examples: :gh:`yes <chipsalliance/f4pga-examples/blob/main/xc7/counter_test/flow.json>`
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* Quicklogic EOS-S3 (yosys+VPR flow) (**WIP**, see :ghsharp:`577`)
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* Synthesis tool: yosys
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* PnR tool: VPR
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* bitstream generation: yes (qlfasm)
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* analysis: ?
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* used in f4pga-examples: no
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* Lattice ICE40 (yosys+nextpnr flow) (**WIP**, see :ghsharp:`585`)
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* Synthesis tool: yosys
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* PnR tool: nextpnr
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* bitstream generation: yes (icepack)
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* used in f4pga-examples: no
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* Quicklogic k4n8 (Unverified, not officially supported. Might work after some tinkering.)
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* Synthesis tool: yosys
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* PnR tool: VPR
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* bitstream generation: yes (qlf_fasm)
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* used in f4pga-examples: no
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* Incremental builds support
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* Support for multiple configurations for a single project
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* Can be used as a python interface to _F4PGA_, however there's no official _API_ at the moment.
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@ -17,9 +17,24 @@ The scope of Python F4PGA is threefold:
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Therefore, it's still a *pre-alpha* and the codebase, commands and flows are subject to change.
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It is strongly suggested not to rely on Python F4PGA until this note is updated/removed.
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.. toctree::
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This is the current in-development FPGA-oriented build system that's provided with f4pga.
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README
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This package aims to provide a unified front-end for executing *verilog-to-bitstream* and
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other flows for various FPGA platforms. It's meant as a future replacement of
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``symbiflow_*`` shell scripts.
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It contains *EDA* tool wrappers that provide meta-data about the tools, utilities
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related to tracking files and inspection of data used within the flows, scripts used by
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tools within flows, a dependency resolution algorithm and flow templates for various devices.
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The basic usage requires creation of a ``flow.json`` file describing the FPGA-oriented project.
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You can take
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:gh:`one from the f4pga-examples repository <chipsalliance/f4pga-examples/blob/main/xc7/counter_test/flow.json>`
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as a reference. Alternatively there's a way to configure a flow with command-line parameters only.
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Once you have your flow created, run ``f4pga build -f flow.json`` to build a default target.
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To learn more about the package and its usage, visit :doc:`Usage`.
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References
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==========
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@ -59,10 +59,12 @@ Table of Contents
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.. toctree::
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:caption: Python utils
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:caption: f4pga Python utils
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:maxdepth: 2
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f4pga/index
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f4pga/Status
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f4pga/Contributing
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f4pga/Usage
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f4pga/modules/index
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f4pga/DevNotes
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