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f4pga: do not use wildcard imports (#617)

This commit is contained in:
Unai Martinez-Corral 2022-08-16 19:10:18 +02:00 committed by GitHub
parent 2d6650fd0e 482dbb854c
commit f4a85507a3
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GPG Key ID: 4AEE18F83AFDEB23
11 changed files with 90 additions and 108 deletions
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4
f4pga/__init__.py
View File

@ -48,13 +48,13 @@ from colorama import Fore, Style
from f4pga.common import (
F4PGAException,
ResolutionEnv,
deep,
fatal,
scan_modules,
set_verbosity_level,
sfprint,
sub as common_sub
)
from f4pga.module import *
from f4pga.cache import F4Cache
from f4pga.flow_config import (
ProjectFlowConfig,
@ -63,7 +63,7 @@ from f4pga.flow_config import (
open_project_flow_cfg,
verify_platform_name
)
from f4pga.module_runner import *
from f4pga.module_runner import ModRunCtx, module_map, module_exec
from f4pga.module_inspector import get_module_info
from f4pga.stage import Stage
from f4pga.argparser import setup_argparser, get_cli_flow_config

13
f4pga/common_modules/analysis.py
View File

@ -18,9 +18,8 @@
# SPDX-License-Identifier: Apache-2.0
from pathlib import Path
from shutil import move as sh_mv
from f4pga.common import *
from f4pga.common import vpr_specific_values, vpr as common_vpr, VprArgs
from f4pga.module import Module, ModuleContext
@ -42,12 +41,10 @@ class analysisModule(Module):
def execute(self, ctx: ModuleContext):
build_dir = str(Path(ctx.takes.eblif).parent)
vpr_options = []
if ctx.values.vpr_options:
vpr_options = options_dict_to_list(ctx.values.vpr_options)
vpr_options = options_dict_to_list(ctx.values.vpr_options) if ctx.values.vpr_options else []
yield 'Analysis with VPR...'
vpr(
common_vpr(
'analysis',
VprArgs(
ctx.share,
@ -59,10 +56,10 @@ class analysisModule(Module):
)
if ctx.is_output_explicit('merged_post_implementation_v'):
sh_mv(analysis_merged_post_implementation_file(ctx), ctx.outputs.merged_post_implementation_v)
Path(analysis_merged_post_implementation_file(ctx)).rename(ctx.outputs.merged_post_implementation_v)
if ctx.is_output_explicit('post_implementation_v'):
sh_mv(analysis_post_implementation_file(ctx), ctx.outputs.post_implementation_v)
Path(analysis_post_implementation_file(ctx)).rename(ctx.outputs.post_implementation_v)
yield 'Saving log...'
save_vpr_log('analysis.log', build_dir=build_dir)

11
f4pga/common_modules/fasm.py
View File

@ -18,9 +18,8 @@
# SPDX-License-Identifier: Apache-2.0
from pathlib import Path
from shutil import move as sh_mv
from f4pga.common import vpr_specific_values, VprArgs, get_verbosity_level, sub
from f4pga.common import vpr_specific_values, VprArgs, get_verbosity_level, sub as common_sub
from f4pga.module import Module, ModuleContext
@ -58,11 +57,11 @@ class FasmModule(Module):
else:
yield 'Generating FASM...'
sub(*s, cwd=build_dir)
common_sub(*s, cwd=build_dir)
default_fasm_output_name = f'{(Path(build_dir)/ctx.values.top)!s}.fasm'
if default_fasm_output_name != ctx.outputs.fasm:
sh_mv(default_fasm_output_name, ctx.outputs.fasm)
default_fasm_output_name = Path(build_dir)/ f'{ctx.values.top}.fasm'
if str(default_fasm_output_name) != ctx.outputs.fasm:
default_fasm_output_name.rename(ctx.outputs.fasm)
if ctx.takes.fasm_extra:
yield 'Appending extra FASM...'

3
f4pga/common_modules/generic_script_wrapper.py
View File

@ -57,7 +57,6 @@ Accepted module parameters:
# TODO: `environment` input kind
from pathlib import Path
from shutil import move as sh_mv
from re import match as re_match, finditer as re_finditer
from f4pga.common import decompose_depname, deep, get_verbosity_level, sub
@ -183,7 +182,7 @@ class GenericScriptWrapperModule(Module):
file = ctx.r_env.resolve(file, final=True)
target = ctx.r_env.resolve(target, final=True)
if target != file:
sh_mv(file, target)
Path(file).rename(target)
def _init_outputs(self, output_defs: 'dict[str, dict[str, str]]'):
self.stdout_target = None

3
f4pga/common_modules/io_rename.py
View File

@ -40,7 +40,6 @@ Accepted module parameters:
"""
from f4pga.common import *
from f4pga.module import Module, ModuleContext
from f4pga.module_runner import get_module
@ -123,4 +122,4 @@ class IORenameModule(Module):
if hasattr(module, 'prod_meta'):
self.prod_meta = _switch_keys(module.prod_meta, self.rename_produces)
ModuleClass = IORenameModule
ModuleClass = IORenameModule

2
f4pga/common_modules/mkdirs.py
View File

@ -26,6 +26,7 @@ the dependency algorithm to lazily create the directories if they become necessa
"""
from pathlib import Path
from f4pga.module import Module, ModuleContext
@ -49,4 +50,5 @@ class MkDirsModule(Module):
self.values = []
self.deps_to_produce = params
ModuleClass = MkDirsModule

16
f4pga/common_modules/pack.py
View File

@ -18,10 +18,8 @@
# SPDX-License-Identifier: Apache-2.0
from pathlib import Path
from os import remove as os_remove
from shutil import move as sh_mv
from f4pga.common import *
from f4pga.common import vpr_specific_values, noisy_warnings, vpr as common_vpr, VprArgs
from f4pga.module import Module, ModuleContext
@ -44,7 +42,7 @@ class PackModule(Module):
build_dir = Path(ctx.outputs.net).parent
yield 'Packing with VPR...'
vpr(
common_vpr(
'pack',
VprArgs(
ctx.share,
@ -55,19 +53,19 @@ class PackModule(Module):
cwd=str(build_dir)
)
og_log = str(build_dir / 'vpr_stdout.log')
og_log = build_dir / 'vpr_stdout.log'
yield 'Moving/deleting files...'
if ctx.outputs.pack_log:
sh_mv(og_log, ctx.outputs.pack_log)
og_log.rename(ctx.outputs.pack_log)
else:
os_remove(og_log)
og_log.unlink()
if ctx.outputs.timing_rpt:
sh_mv(str(build_dir / DEFAULT_TIMING_RPT), ctx.outputs.timing_rpt)
(build_dir / DEFAULT_TIMING_RPT).rename(ctx.outputs.timing_rpt)
if ctx.outputs.util_rpt:
sh_mv(str(build_dir / DEFAULT_UTIL_RPT), ctx.outputs.util_rpt)
(build_dir / DEFAULT_UTIL_RPT).rename(ctx.outputs.util_rpt)
def __init__(self, _):
self.name = 'pack'

54
f4pga/common_modules/place.py
View File

@ -18,54 +18,55 @@
# SPDX-License-Identifier: Apache-2.0
from pathlib import Path
import os
from shutil import move as sh_mv
from re import match as re_match
from f4pga.common import *
from f4pga.common import vpr_specific_values, vpr as common_vpr, VprArgs, save_vpr_log
from f4pga.module import Module, ModuleContext
def default_output_name(place_constraints):
p = place_constraints
m = re_match('(.*)\\.[^.]*$', place_constraints)
if m:
return m.groups()[0] + '.place'
return f'{p}.place'
return f'{place_constraints}.place'
def place_constraints_file(ctx: ModuleContext):
p = ctx.takes.place_constraints
if p:
return p, False
p = ctx.takes.io_place
if p:
return p, False
if ctx.takes.place_constraints:
return ctx.takes.place_constraints, False
if ctx.takes.io_place:
return ctx.takes.io_place, False
return f'{Path(ctx.takes.eblif).stem}.place', True
class PlaceModule(Module):
def map_io(self, ctx: ModuleContext):
mapping = {}
p, _ = place_constraints_file(ctx)
mapping['place'] = default_output_name(p)
return mapping
return {
'place': default_output_name(p)
}
def execute(self, ctx: ModuleContext):
place_constraints, dummy = place_constraints_file(ctx)
place_constraints = os.path.realpath(place_constraints)
place_constraints = Path(place_constraints).resolve()
if dummy:
with open(place_constraints, 'wb') as f:
f.write(b'')
with place_constraints.open('wb') as wfptr:
wfptr.write(b'')
build_dir = str(Path(ctx.takes.eblif).parent)
vpr_options = ['--fix_clusters', place_constraints]
build_dir = Path(ctx.takes.eblif).parent
yield 'Running VPR...'
vprargs = VprArgs(ctx.share, ctx.takes.eblif, ctx.values,
sdc_file=ctx.takes.sdc, vpr_extra_opts=vpr_options)
vpr('place', vprargs, cwd=build_dir)
common_vpr(
'place',
VprArgs(
ctx.share,
ctx.takes.eblif,
ctx.values,
sdc_file=ctx.takes.sdc,
vpr_extra_opts=['--fix_clusters', place_constraints]
),
cwd=str(build_dir)
)
# VPR names output on its own. If user requested another name, the
# output file should be moved.
@ -75,11 +76,10 @@ class PlaceModule(Module):
# modules may produce some temporary files with names that differ from
# the ones in flow configuration.
if ctx.is_output_explicit('place'):
output_file = default_output_name(place_constraints)
sh_mv(output_file, ctx.outputs.place)
Path(default_output_name(str(place_constraints))).rename(ctx.outputs.place)
yield 'Saving log...'
save_vpr_log('place.log', build_dir=build_dir)
save_vpr_log('place.log', build_dir=str(build_dir))
def __init__(self, _):
self.name = 'place'

42
f4pga/common_modules/place_constraints.py
View File

@ -18,7 +18,7 @@
# SPDX-License-Identifier: Apache-2.0
from pathlib import Path
from f4pga.common import *
from f4pga.common import sub as common_sub
from f4pga.module import Module, ModuleContext
@ -29,31 +29,23 @@ class PlaceConstraintsModule(Module):
}
def execute(self, ctx: ModuleContext):
arch_dir = str(Path(ctx.share) / 'arch')
arch_def = str(Path(arch_dir) / ctx.values.device / 'arch.timing.xml')
database = sub('prjxray-config').decode().replace('\n', '')
yield 'Generating .place...'
extra_opts: 'list[str]'
if ctx.values.extra_opts:
extra_opts = options_dict_to_list(ctx.values.extra_opts)
else:
extra_opts = []
data = sub(*(['python3', ctx.values.script,
'--net', ctx.takes.net,
'--arch', arch_def,
'--blif', ctx.takes.eblif,
'--input', ctx.takes.io_place,
'--db_root', database,
'--part', ctx.values.part_name]
+ extra_opts))
yield 'Saving place constraint data...'
with open(ctx.outputs.place_constraints, 'wb') as f:
f.write(data)
with Path(ctx.outputs.place_constraints).open('wb') as wfptr:
wfptr.write(
common_sub(*(
[
'python3', ctx.values.script,
'--net', ctx.takes.net,
'--arch', str(Path(ctx.share) / 'arch' / ctx.values.device / 'arch.timing.xml'),
'--blif', ctx.takes.eblif,
'--input', ctx.takes.io_place,
'--db_root', common_sub('prjxray-config').decode().replace('\n', ''),
'--part', ctx.values.part_name
] + (
options_dict_to_list(ctx.values.extra_opts) if ctx.values.extra_opts else []
)
))
)
def __init__(self, _):
self.name = 'place_constraints'

21
f4pga/common_modules/route.py
View File

@ -18,31 +18,28 @@
# SPDX-License-Identifier: Apache-2.0
from pathlib import Path
from shutil import move as sh_mv
from f4pga.common import *
from f4pga.common import vpr_specific_values, vpr as common_vpr, VprArgs, options_dict_to_list, save_vpr_log
from f4pga.module import Module, ModuleContext
def route_place_file(ctx: ModuleContext):
return str(Path(ctx.takes.eblif).with_suffix('.route'))
return Path(ctx.takes.eblif).with_suffix('.route')
class RouteModule(Module):
def map_io(self, ctx: ModuleContext):
return {
'route': route_place_file(ctx)
'route': str(route_place_file(ctx))
}
def execute(self, ctx: ModuleContext):
build_dir = str(Path(ctx.takes.eblif).parent)
build_dir = Path(ctx.takes.eblif).parent
vpr_options = []
if ctx.values.vpr_options:
vpr_options = options_dict_to_list(ctx.values.vpr_options)
vpr_options = options_dict_to_list(ctx.values.vpr_options) if ctx.values.vpr_options else []
yield 'Routing with VPR...'
vpr(
common_vpr(
'route',
VprArgs(
ctx.share,
@ -50,14 +47,14 @@ class RouteModule(Module):
ctx.values,
sdc_file=ctx.takes.sdc
),
cwd=build_dir
cwd=str(build_dir)
)
if ctx.is_output_explicit('route'):
sh_mv(route_place_file(ctx), ctx.outputs.route)
route_place_file(ctx).rename(ctx.outputs.route)
yield 'Saving log...'
save_vpr_log('route.log', build_dir=build_dir)
save_vpr_log('route.log', build_dir=str(build_dir))
def __init__(self, _):
self.name = 'route'

29
f4pga/common_modules/synth.py
View File

@ -17,9 +17,10 @@
#
# SPDX-License-Identifier: Apache-2.0
import os
from os import environ
from pathlib import Path
from f4pga.common import *
from f4pga.common import decompose_depname, get_verbosity_level, sub as common_sub
from f4pga.module import Module, ModuleContext
@ -43,7 +44,7 @@ def yosys_synth(tcl, tcl_env, verilog_files=[], read_verilog_args=None, log=None
optional = []
if log:
optional += ['-l', log]
env = os.environ.copy()
env = environ.copy()
env.update(tcl_env)
tcl = f'tcl {tcl}'
@ -57,14 +58,14 @@ def yosys_synth(tcl, tcl_env, verilog_files=[], read_verilog_args=None, log=None
verilog_files = []
# Execute YOSYS command
return sub(*(['yosys', '-p', tcl] + optional + verilog_files), env=env)
return common_sub(*(['yosys', '-p', tcl] + optional + verilog_files), env=env)
def yosys_conv(tcl, tcl_env, synth_json):
# Set up environment for TCL weirdness
env = os.environ.copy()
env = environ.copy()
env.update(tcl_env)
return sub('yosys', '-p', f'read_json {synth_json}; tcl {tcl}', env=env)
return common_sub('yosys', '-p', f'read_json {synth_json}; tcl {tcl}', env=env)
class SynthModule(Module):
@ -75,13 +76,13 @@ class SynthModule(Module):
top = ctx.values.top
if ctx.takes.build_dir:
top = os.path.join(ctx.takes.build_dir, top)
top = str(Path(ctx.takes.build_dir) / top)
mapping['eblif'] = top + '.eblif'
mapping['fasm_extra'] = top + '_fasm_extra.fasm'
mapping['json'] = top + '.json'
mapping['synth_json'] = top + '_io.json'
b_path = os.path.dirname(top)
b_path = Path(top).parent.name
for extra in self.extra_products:
name, spec = decompose_depname(extra)
@ -91,9 +92,7 @@ class SynthModule(Module):
f'(?) specifier. Product causing this error: `{extra}`.'
)
elif spec == 'req':
mapping[name] = \
os.path.join(b_path,
ctx.values.device + '_' + name + '.' + name)
mapping[name] = str(Path(b_path) / f'{ctx.values.device}_{name}.{name}')
return mapping
@ -113,12 +112,12 @@ class SynthModule(Module):
ctx.values.read_verilog_args, ctx.outputs.synth_log)
yield f'Splitting in/outs...'
sub('python3', str(split_inouts), '-i', ctx.outputs.json, '-o',
common_sub('python3', str(split_inouts), '-i', ctx.outputs.json, '-o',
ctx.outputs.synth_json)
if not os.path.isfile(ctx.produces.fasm_extra):
with open(ctx.produces.fasm_extra, 'w') as f:
f.write('')
if not Path(ctx.produces.fasm_extra).is_file():
with Path(ctx.produces.fasm_extra).open('w') as wfptr:
wfptr.write('')
yield f'Converting...'
yosys_conv(str(conv_tcl), tcl_env, ctx.outputs.synth_json)