Hardware
/
f4pga
mirror of https://github.com/chipsalliance/f4pga.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
FOSS Flow For FPGA
163 Commits 3 Branches 0 Tags 32 MiB
Python 94.3%
Shell 2.9%
Tcl 2.2%
XSLT 0.3%
VHDL 0.1%
Other 0.2%
Go to file
dependabot-preview[bot] 0b70df0e5c
Bump source/vtr-verilog-to-routing from `5c324d1` to `bb0ba83` 
Bumps [source/vtr-verilog-to-routing](https://github.com/SymbiFlow/vtr-verilog-to-routing) from `5c324d1` to `bb0ba83`.
- [Release notes](https://github.com/SymbiFlow/vtr-verilog-to-routing/releases)
- [Commits](5c324d19b0...bb0ba83ea0)

Signed-off-by: dependabot-preview[bot] <support@dependabot.com>
 		2020-01-30 06:35:13 +00:00
doxygen Add support for documenting C++ with Sphinx 2019-10-18 09:44:31 +02:00
source Bump source/vtr-verilog-to-routing from `5c324d1` to `bb0ba83` 2020-01-30 06:35:13 +00:00
.gitignore Overwriting old documentation without DCO 2019-04-05 07:56:47 -07:00
.gitmodules Replace VPR abstract with official VPR documentation 2019-09-25 21:50:21 +02:00
COPYING Adding missing ISC license file 2019-11-20 11:29:06 -08:00
Makefile Enable conda environment support 2019-10-16 18:45:52 +00:00
enter-env.sh Enable conda environment support 2019-10-16 18:45:52 +00:00
environment.yml Add Symbolator for generating symbols of verilog models 2019-10-21 13:35:45 +00:00
readthedocs.yml Check out submodules recursively 2019-10-17 12:27:12 +00:00
requirements.txt Add Symbolator for generating symbols of verilog models 2019-10-21 13:35:45 +00:00