f4pga/test/vhdl/counter/arty_35.json

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{
"default_part": "XC7A35TCSG324-1",
"values": {
"top": "Arty_Counter"
},
"dependencies": {
"sources": [
"Arty_Counter.v"
],
"synth_log": "synth.log",
"pack_log": "pack.log"
},
"XC7A35TCSG324-1": {
"default_target": "bitstream",
"dependencies": {
"build_dir": "build/arty_35",
"xdc": [
"../../constraints/arty.xdc"
]
},
"values": {
"part": "xc7a35tcpg236-1"
}
}
}