82 lines
3.7 KiB
ReStructuredText
82 lines
3.7 KiB
ReStructuredText
Introduction
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============
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F4PGA is a Open Source Verilog-to-Bitstream FPGA synthesis flow,
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currently targeting Xilinx 7-Series, Lattice iCE40 and Lattice ECP5 FPGAs.
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Think of it as the GCC of FPGAs.
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The project aim is to design tools that are highly extendable and multiplatform.
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EDA Tooling Ecosystem
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---------------------
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For both ASIC- and FPGA-oriented EDA tooling, there are three major areas that
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the workflow needs to cover: hardware description, frontend and backend.
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Hardware description languages are generally open, with both established HDLs
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such as Verilog and VHDL and emerging software-inspired paradigms like
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`Chisel <https://chisel.eecs.berkeley.edu/>`_,
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`SpinalHDL <https://spinalhdl.github.io/SpinalDoc-RTD/>`_ or
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`Migen <https://m-labs.hk/gateware/migen/>`_.
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The major problem lies however in the front- and backend, where previously
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there was no established standard, vendor-neutral tooling that would cover
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all the necessary components for an end-to-end flow.
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This pertains both to ASIC and FPGA workflows, although F4PGA focuses
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on the latter (some parts of F4PGA will also be useful in the former).
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.. figure:: _static/images/EDA.svg
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Project structure
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-----------------
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To achieve F4PGA's goal of a complete FOSS FPGA toolchain, a number of tools and projects are necessary to provide all
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the needed components of an end-to-end flow.
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Thus, F4PGA serves as an umbrella project for several activities, the central of which pertains to the creation of
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so-called FPGA "architecture definitions", i.e. documentation of how specific FPGAs work internally.
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More information can be found in the :doc:`F4PGA Architecture Definitions <arch-defs:index>` project.
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Those definitions and serve as input to backend tools like
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`nextpnr <https://github.com/YosysHQ/nextpnr>`_ and
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`Verilog to Routing <https://verilogtorouting.org/>`_, and frontend tools
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like `Yosys <http://www.clifford.at/yosys/>`_. They are created within separate
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collaborating projects targeting different FPGAs - :doc:`Project X-Ray
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<prjxray:index>` for Xilinx 7-Series, `Project IceStorm
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<http://www.clifford.at/icestorm/>`_ for Lattice iCE40 and :doc:`Project Trellis
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<prjtrellis:index>` for Lattice ECP5 FPGAs.
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.. figure:: _static/images/parts.svg
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Current status of bitstream documentation
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-----------------------------------------
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.. table::
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:align: center
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:widths: 40 20 20 20
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+-----------------+----------+----------+---------+
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| Projects | IceStorm | X-Ray | Trellis |
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+=================+==========+==========+=========+
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| **Basic Tiles** |
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+-----------------+----------+----------+---------+
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| Logic | Yes | Yes | Yes |
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+-----------------+----------+----------+---------+
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| Block RAM | Yes | Partial | N/A |
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+-----------------+----------+----------+---------+
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| **Advanced Tiles** |
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+-----------------+----------+----------+---------+
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| DSP | Yes | No | Yes |
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+-----------------+----------+----------+---------+
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| Hard Blocks | Yes | No | Yes |
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+-----------------+----------+----------+---------+
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| Clock Tiles | Yes | Partial | Yes |
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+-----------------+----------+----------+---------+
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| IO Tiles | Yes | Partial | Yes |
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+-----------------+----------+----------+---------+
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| **Routing** |
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+-----------------+----------+----------+---------+
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| Logic | Yes | Yes | Yes |
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+-----------------+----------+----------+---------+
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| Clock | Yes | Partial | Yes |
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+-----------------+----------+----------+---------+
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