f4pga/source
Robert Winkler 2db5d5beb6 Add technology mapping description
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
2020-09-28 11:25:53 +02:00
..
fasm@4857dde757 Bump source/fasm from `5453062` to `4857dde` 2020-06-12 06:29:32 +00:00
images Add SymbiFlow toolchain description 2019-09-25 21:50:21 +02:00
prjtrellis@f93243b000 Bump source/prjtrellis from `cada34d` to `f93243b` 2020-06-30 06:33:07 +00:00
prjxray@58df67f243 Bump source/prjxray from `0339695` to `58df67f` 2020-08-31 05:52:10 +00:00
symbiflow-arch-defs@6e6e8c7ce9 Bump source/symbiflow-arch-defs from `8b9105d` to `6e6e8c7` 2020-09-21 05:50:18 +00:00
toolchain-desc Add technology mapping description 2020-09-28 11:25:53 +02:00
vtr-verilog-to-routing@f1a3bcc2a8 Bump source/vtr-verilog-to-routing from `82b720d` to `f1a3bcc` 2020-09-17 05:45:50 +00:00
conf.py Add sphinx-verilog-domain to Sphinx configuration 2020-09-22 14:37:30 +02:00
index.rst Use fasm specification from fasm repository 2019-09-25 21:50:21 +02:00
introduction.rst Add more information about SymbiFlow to introduction 2019-09-19 09:38:40 +02:00
toolchain-desc.rst Replace VPR abstract with official VPR documentation 2019-09-25 21:50:21 +02:00