70 lines
3.6 KiB
ReStructuredText
70 lines
3.6 KiB
ReStructuredText
How it works
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############
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To understand how F4PGA works, it is best to start with an overview of the general EDA tooling ecosystem and then
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proceed to see what the F4PGA project consists of.
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EDA Tooling Ecosystem
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=====================
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For both ASIC- and FPGA-oriented EDA tooling, there are three major areas that
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the workflow needs to cover: hardware description, frontend and backend.
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Hardware description languages are generally open, with both established HDLs
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such as Verilog and VHDL and emerging software-inspired paradigms like
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`Chisel <https://chisel.eecs.berkeley.edu/>`_,
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`SpinalHDL <https://spinalhdl.github.io/SpinalDoc-RTD/>`_ or
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`Migen <https://m-labs.hk/gateware/migen/>`_.
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The major problem lies however in the front- and backend, where previously
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there was no established standard, vendor-neutral tooling that would cover
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all the necessary components for an end-to-end flow.
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This pertains both to ASIC and FPGA workflows, although F4PGA focuses
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on the latter (some parts of F4PGA will also be useful in the former).
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.. figure:: _static/images/EDA.svg
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Project structure
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=================
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To achieve F4PGA's goal of a complete FOSS FPGA toolchain, a number of tools and projects are necessary to provide all
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the needed components of an end-to-end flow.
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Thus, F4PGA serves as an umbrella project for several activities, the central of which pertains to the creation of
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so-called FPGA "architecture definitions", i.e. documentation of how specific FPGAs work internally.
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More information can be found in the :doc:`F4PGA Architecture Definitions <arch-defs:index>` project.
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Those definitions and serve as input to backend tools like
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`nextpnr <https://github.com/YosysHQ/nextpnr>`_ and
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`Verilog to Routing <https://verilogtorouting.org/>`_, and frontend tools
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like `Yosys <http://www.clifford.at/yosys/>`_. They are created within separate
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collaborating projects targeting different FPGAs - :doc:`Project X-Ray
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<prjxray:index>` for Xilinx 7-Series, `Project IceStorm
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<http://www.clifford.at/icestorm/>`_ for Lattice iCE40 and :doc:`Project Trellis
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<prjtrellis:index>` for Lattice ECP5 FPGAs.
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.. figure:: _static/images/parts.svg
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The F4PGA toolchain consists of logic synthesis and implementation tools, as well as chip documentation projects for
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chips of various vendors.
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To prepare a working bitstream for a particular FPGA chip, the toolchain goes through the following stages:
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* First, a description of the FPGA chip is created with the information from the relevant bitstream documentation
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project.
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This part is done within the `F4PGA Architecture Definitions <https://github.com/chipsalliance/f4pga-arch-defs>`__.
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The project prepares information about the timings and resources available in the chip needed at the implementation
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stage, as well as techmaps for the synthesis tools.
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* The second step is logic synthesis.
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It is carried out in the Yosys framework, which expresses the input Verilog file by means of the block and connection
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types available in the chosen chip.
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* The next step is implementation.
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Placement and routing tools put individual blocks from the synthesis description in the specific chip locations and
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create paths between them.
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To do that, F4PGA uses either `nextpnr <https://github.com/YosysHQ/nextpnr>`__ or `Verilog to Routing <https://github.com/verilog-to-routing/vtr-verilog-to-routing>`__.
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* Finally, the design properties are translated into a set of features available in the given FPGA chip.
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These features are saved in the `fasm format <https://github.com/chipsalliance/fasm>`__, which is developed as part of
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F4PGA.
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The fasm file is then translated to bitstream using the information from the bitstream documentation projects.
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