160 lines
6.9 KiB
ReStructuredText
160 lines
6.9 KiB
ReStructuredText
FPGA Design Flow
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================
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SymbiFlow is an end-to-end FPGA synthesis toolchain, because of that it provides
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all the necessary tools to convert input Verilog design into a final bitstream.
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It is simple to use however, the whole synthesis and implementation process
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is not trivial.
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The final bitstream format depends on the used platform.
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What's more, every platform has different resources and even if some of them
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provide similar functionality, they can be implemented in a different way.
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In order to be able to match all that variety of possible situations,
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the creation of the final bitstream is divided into few steps.
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SymbiFlow uses different programs to create the bitstream and is
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responsible for their proper integration. The procedure of converting
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Verilog file into the bitstream is described in the next sections.
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.. figure:: ../_static/images/toolchain-flow.svg
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:align: center
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Symbiflow Toolchain design flow
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Synthesis
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---------
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Synthesis is the process of converting input Verilog file into a netlist,
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which describes the connections between different block available on the
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desired FPGA chip. However, it is worth to notice that these are only
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logical connections. So the synthesized model is only a draft of the final
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design, made with the use of available resources.
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RTL Generation
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++++++++++++++
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the input Verilog file is often really complicated. Usually it is written in
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a way that it is hard to distinguish the digital circuit standing behind
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the implemented functionality. Designers often use a so-called
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*Behavioral Level* of abstraction, in their designs, which means that the whole
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description is mostly event-driven. In Verilog, support for behavioral models
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is made with use of ``always`` statements.
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However, FPGA mostly consist of Look Up Tables (LUT) and flip-flops.
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Look Up Tables implement only the functionality of logic gates.
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Due to that, the synthesis process has to convert the complicated
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Behavioral model to a simpler description.
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Firstly, the design is described in terms of registers and logical operations.
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This is the so-called *Register-Transfer Level* (*RTL*).
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Secondly, in order to simplify the design even more, some complex logic is
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rewritten in the way that the final result contain only logic gates
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and registers. This model is on *Logical Gate level* of abstraction.
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The process of simplification is quite complicated, because of that it often
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demands additional simulations between mentioned steps to prove that the input
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design is equivalent to its simplified form.
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Technology mapping
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++++++++++++++++++
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FPGAs from different architectures may have different architecture. For example,
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they may contain some complicated functional blocks (i.e. RAM, DSP blocks)
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and even some of the basic blocks like LUT tables and flip-flops may vary
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between chips. Because of that, there is a need to describe the final design
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in terms of platform-specific resources. This is the next step in the process
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of synthesis. The simplified description containing i.e. logic gates, flip-flops
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and a few more complicated blocks like RAM is taken and used "general" blocks
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are substituted with that physically located in the chosen FPGA.
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The vendor-specific definitions of these blocks are often located
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in a separate library.
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Optimization
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++++++++++++
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Optimization is the key factor that allows to better utilize resources
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of an FPGA. There are some universal situations in which the design
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can be optimized, for example by substituting a bunch of logic gates
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in terms of fewer, different gates. However, some operations can be performed
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only after certain steps i.e. after technology mapping.
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As a result, optimization is an integral part of most of the synthesis steps.
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Synthesis in SymbiFlow
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++++++++++++++++++++++
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In the SymbiFlow toolchain synthesis is made with the use of Yosys,
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that is able to perform all the mentioned steps and convert Verilog to netlist
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description. The result of these steps is written to a file in ``.eblif``
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format.
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Place & Route
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-------------
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The Synthesis process results in an output containing logical elements
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available on the desired FPGA chip with the specified connections between them.
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However, it does not specify the physical layout of those elements in the
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final design. The goal of the Place and Route (PnR) process is to take the
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synthesized design and implement it into the target FPGA device. The PnR tool
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needs to have information about the physical composition of the device, routing
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paths between the different logical blocks and signal propagation timings.
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The working flow of different PnR tools may vary, however, the process presented
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below represents the typical one, adopted by most of these tools. Usually, it
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consists of four steps - packing, placing, routing and analysis.
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Packing
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+++++++
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In the first step, the tool collects and analyzes the primitives present
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in the synthesized design (e.g. Flip-Flops, Muxes, Carry-chains, etc), and
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organizes them in clusters, each one belonging to a physical tile of the device.
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The PnR tool makes the best possible decision, based on the FPGA routing
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resources and timings between different points in the chip.
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Placing
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+++++++
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After having clustered all the various primitives into the physical tiles of the
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device, the tool begins the placement process. This step consists in assigning a
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physical location to every cluster generated in the packing stage. The choice of
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the locations is based on the chosen algorithm and on the user's parameters, but
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generally, the final goal is to find the best placement that allows the routing
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step to find more optimal solutions.
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Routing
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+++++++
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Routing is one of the most demanding tasks of the the whole process.
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All possible connections between the placed blocks and the information on
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the signals propagation timings, form a complex graph.
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The tool tries to find the optimal path connecting all the placed
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clusters using the information provided in the routing graph. Once all the nets
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have been routed, an output file containing the implemented design is produced.
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Analysis
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++++++++
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This last step usually checks the whole design in terms of timings and power
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consumption.
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Place & Route in SymbiFlow
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++++++++++++++++++++++++++
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The SymbiFlow Project uses two different tools for the PnR process - ``nextpnr``
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and ``Versatile Place and Route`` (VPR). Both of them write their final result
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to a file in the ``.fasm`` format.
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Bitstream translation
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---------------------
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The routing process results in an output file specifying the used blocks
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and routing paths. It contains the resources that needs to be instantiated
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on the FPGA chip, however, the output format is not understood
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by the FPGA chip itself.
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In the last step, the description of the chip is translated into
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the appropriate format, suitable for the chosen FPGA.
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That final file contains instructions readable by the configuration block of
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the desired chip.
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Documenting the bitstream format for different FPGA chips is one of the
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most important tasks in the SymbiFlow Project!
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